Abstract: A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs.

Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

Abstract: In a semiconductor physical quantity sensor of electrostatic capacitance type, mutually facing peripheral areas (bonding areas) of a glass substrate and a silicon substrate are contacted for anodic bonding, while at the same time, both substrates have an anodic bonding voltage applied therebetween so as to be integrated. A fixed electrode is formed on a bonding face-side surface of the silicon substrate, while a movable electrode is formed on a bonding face-side surface of the semiconductor substrate. An equipotential wiring, which short-circuits the fixed electrode to the movable electrode as a countermeasure to discharge in anodic bonding, is formed on the bonding face-side surface of the glass substrate inside the bonding area before the anodic bonding. After the anodic bonding, the equipotential wiring is cut and removed.

Abstract: A micro-electro-mechanical systems (MEMS) device includes a back-plate substrate, having an intended region formed with a plurality of perforating holes. A first structural dielectric layer, disposed on the back-plate substrate, wherein the dielectric layer having an opening above the intended region. An etching stop layer, disposed over the first structural dielectric layer. A second structural dielectric layer, formed over the back-plate substrate. The etching stop layer and the second structural dielectric layer form at least a part of a micro-machine diaphragm, and cover over the opening of the first structural dielectric layer to form a chamber between the micro-machine diaphragm and the back-plate substrate.

Abstract: A method of manufacturing a semiconductor device forms an N? diffusion layer to be a source/drain region of a grooved transistor simultaneously with an N? diffusion layer of a channel region directly under a gate electrode of an antifuse element. The formation of the N? diffusion layer directly under the gate electrode of the antifuse element stabilizes electrical connection between the gate electrode and the source/drain diffusion region even during writing with a low write voltage.

Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.

Abstract: In order to manufacture a highly reliable and compact TFT, it is an object of the present invention to provide a method for manufacturing a semiconductor device for forming a gate electrode, a source wiring and a drain wiring with high reliability, and a semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film is formed over a substrate having an insulated surface, a gate insulating film is formed over the semiconductor film, a gate electrode is formed over the gate insulating film, and a nitride film is formed over the surface of the gate electrode by nitriding the surface of the gate electrode by using high-density plasma.

Abstract: A semiconductor defect type determination method and structure. The method includes providing a semiconductor wafer comprising a first field effect transistor (FET) comprising a first type of structure and a second FET comprising a second different type of structure. A first procedure is performed to determine if a first current flow exists between a first conductive layer formed on the first FET and a second conductive layer formed on the first FET. A second procedure is performed to determine if a second current flow exists between a third conductive layer formed the second FET and a fourth conductive layer formed on the second FET. A determination is made from combining results of the first procedure and results of the second procedure that the first FET and the second FET each comprise a specified type of defect.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.

Abstract: A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.

Abstract: Provided is a probe card for semiconductor IC test on one principal surface of which are formed a plurality of probe electrodes, such as bump electrodes (5), and which has, in a peripheral portion thereof, a thin film sheet (9) fixed to a support, such as a ceramics ring (7). A local tension-changed portion (12) is formed in the thin film sheet (9) fixed to the ceramics ring (7) so that a tensile strain is generated, and the plurality of bump electrodes (5) are arranged in prescribed positions that connect electrically to electrodes of each semiconductor IC element of the semiconductor wafer. The tensile strain of the thin film sheet (9) is changed positively and in a sustained manner, whereby the bump electrodes (5) are rearranged in desired positions.

Abstract: By providing a plurality of resistors and a plurality of test patterns within a leakage current test structure, the number of probe pads required for estimating the plurality of test patterns may be significantly reduced, wherein, in some illustrative embodiments, several test patterns may be simultaneously assessed on the basis of two probe pads. Consequently, process parameters and/or design parameters for manufacturing metallization structures of semiconductor devices may be efficiently monitored and controlled.

Abstract: A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surface of a transistor. Next, a trench and a contact hole are formed by etching the dielectric layer so that the upper surface of the transistor is exposed. Then, a contact is formed by embedding a first conductive layer in the contact hole. Next, an etching stop layer is selectively forming on an upper part of the contact. Then, the semiconductor device is blanket-etched such that the first conductive layer remains in the trench. Next, the etching stop layer is removed. Finally, a metal line is formed by embedding a second conductive layer in the trench.

Abstract: A circuit structure has a circuit portion with negative resistance and a test resonator structure. Furthermore, the circuit structure has a unit for coupling the test resonator structure to the circuit portion with negative resistance during testing and for decoupling the test resonator structure from the circuit portion with negative resistance after testing.

Abstract: Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.

Abstract: An automated test equipment interface system, e.g., for attaching a handler to a test head, includes a device interface board assembly. The device interface board assembly includes a stiffener frame having a frame body that is configured for attachment to a test head, alignment brackets connected to the frame body, and cam followers connected to the alignment brackets. The system also includes a docking device. The docking device includes a docking plate that is configured for attachment to a handler, pull-down ramps connected to the docking plate and movable between a retracted position and an extended position, an actuator operable to initiate movement of the pull-down ramps, and a coupling that translates movement of the actuator to corresponding movements of the pull-down ramps.

Abstract: A plurality of calibration structures facilitate calibration of a probing system that includes a differential signal probe having a linear array of probe tips.

Abstract: A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.

Abstract: A method for manufacturing a micro-electromechanical systems (MEMS) device, comprising providing a base layer (10) and a mechanical layer (12) on a substrate (14), providing a sacrificial layer (16) between the base layer (10) and the mechanical layer (12), providing an etch stop layer (18) between the sacrificial layer (16) and the substrate (14), and removing the sacrificial layer (16) by means of dry chemical etching, wherein the dry chemical etching is performed using a fluorine-containing plasma, and the etch stop layer (18) comprises a substantially non-conducting, fluorine chemistry inert material, such as HfO2, ZrO2, Al2O3 or TiO2.

Abstract: A method for forming a contact to a substrate is disclosed. The method includes providing a substrate, the substrate being doped with a first dopant; and diffusing a second dopant into at least a first side of the substrate to form a second dopant region, the first side further including a first side surface area. The method also includes forming a dielectric layer on the first side of the substrate. The method further includes forming a set of composite layer regions on the dielectric layer, wherein each composite layer region of the set of composite layer regions further includes a set of Group IV semiconductor nanoparticles and a set of metal particles. The method also includes heating the set of composite layer regions to a first temperature, wherein at least some composite layer regions of the set of composite layer regions etch through the dielectric layer and form a set of contacts with the second dopant region.