Patents Examined by Karen M Kusumakar
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Patent number: 7602203Abstract: An object of the present invention is to make it possible that a probe for testing electrical characteristics of an object to be tested is easily attached to a support member such as a contactor. A through hole is formed in the contactor. In the probe, a fitting/locking portion which can be fitted in this through hole is formed. The fitting/locking portion is formed to penetrate the through hole of the contactor and to be locked in the contactor in a state that a tip thereof is in contact with a connecting terminal of a printed wiring board. The fitting/locking portion itself is locked in the contactor by hooking a locking portion thereof to an end face on an upper side of the through hole.Type: GrantFiled: March 1, 2006Date of Patent: October 13, 2009Assignee: Tokyo Electron LimitedInventor: Kiyoshi Takekoshi
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Patent number: 7602199Abstract: An apparatus and method for testing large area substrates is described. The large area substrates include patterns of displays and contact points electrically coupled to the displays. The apparatus includes a prober assembly that is movable relative to the large area substrate and may be configured to test various patterns of displays and contact points. The prober assembly is also configured to test fractional sections of the large area substrate. The apparatus also includes a test chamber configured to store at least two prober assemblies within an interior volume.Type: GrantFiled: May 9, 2007Date of Patent: October 13, 2009Assignee: Applied Materials, Inc.Inventors: Benjamin M. Johnston, Sriram Krishnaswami, Hung T. Nguyen, Matthias Brunner, Yong Liu
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Patent number: 7602202Abstract: A semiconductor probe and a method of fabricating the same are provided. The semiconductor probe includes a cantilever doped with first impurities, a resistive tip which protrudes from an end of the cantilever and doped lightly with second impurities, doping control layers formed on both sides of a protruding portion of the resistive tip, and first and second electrode regions formed under the doping control layers and doped heavily with the second impurities.Type: GrantFiled: January 12, 2007Date of Patent: October 13, 2009Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Ju-hwan Jung, Jun-soo Kim, Hyung-cheol Shin, Seung-bum Hong
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Patent number: 7601592Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.Type: GrantFiled: June 9, 2008Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
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Patent number: 7595631Abstract: A chip test system including a probe card, a chip tray and a cover plate fastened on the chip tray. The chip tray comprises a socket, a chip contact area, an extension contact area, and an alignment contact point. The socket loads the testing chip and is customized for the tested chip. The chip contact area has a plurality of chip contact points to electrically contact the chip. The extension contact area has a plurality of extension contact points corresponding to the chip contact points to direct test signals into the chip and direct feedback signals out of the chip. The alignment point provides an alignment location for the probe card during the chip test.Type: GrantFiled: January 11, 2007Date of Patent: September 29, 2009Assignee: Visera Technologies Company LimitedInventors: Sheng-Feng Lu, Yu-Kun Hsiao
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Patent number: 7589515Abstract: [Problem] To permit reduction in the temperature dependence of a sensor, which is ascribable to the temperature dependence of the Verdet constant of a sensor fiber, at a low cost. [Means for Resolution] In a prior-art optical sensor fiber of reflection type, reduction in the temperature dependence of a sensor is coped with by, e.g., duplexing a signal processing circuit and a receiving optical system, so as to execute the mean processing of modulation signals, whereas in this invention, the elimination of the temperature dependence of a modulation signal is realized by selecting a ferromagnetic Faraday rotor 13 so that a modulation degree (Sout) expressed by the ratio between an AC component and a DC component may become constant or within a certain range, so as to especially simplify a configuration and to attain a lower cost.Type: GrantFiled: August 17, 2005Date of Patent: September 15, 2009Assignee: The Tokyo Electric Power Company, IncorporatedInventors: Kiyoshi Kurosawa, Kazuomi Shirakawa
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Patent number: 7583093Abstract: A method for testing an integrated circuit is provided comprising steps of providing at least one first conductive path stretching along an element of the integrated circuit, applying a voltage at a point of the first conductive path, performing a first measurement of the voltage at a point of the first conductive path, and determining whether the integrated circuit is damaged according to the result of the first measurement. Application to the detection of damage due to the sawing or electrical testing of integrated circuits.Type: GrantFiled: August 24, 2007Date of Patent: September 1, 2009Assignee: STMicroelectronics SAInventor: Francois Tailliet
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Patent number: 7583072Abstract: A current sensor for detecting current flowing through a conductive bus bar. A fitting groove is formed in the bus bar. A package is fitted into the fitting groove including a magnetic detection element that detects current flowing through the bus bar. A lead frame is connected to the magnetic detection element and extends out of the package. The bus bar includes a first conductor and a second conductor facing toward the first conductor, with the first and second conductors defining the fitting groove. The magnetic detection element is arranged between the first conductor and the second conductor in a state in which the package is fitted into the fitting groove.Type: GrantFiled: February 1, 2007Date of Patent: September 1, 2009Assignee: Kabushiki Kaisha Tokai Rika Denki SeisakushoInventors: Hitoshi Muraki, Hiroshi Ueno, Kenji Tanaka
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Patent number: 7583101Abstract: A microelectronic resilient structure can comprise a support member and a platform attached to the support member. The platform can comprise a non-conductive, resilient beam that extends away from the support member, and a plurality of conductive members can be disposed on the beams. The conductive members can extend along a length of the beam. A plurality of conductive contact elements can be disposed on the beam and electrically connected to one of the conductive members.Type: GrantFiled: January 18, 2007Date of Patent: September 1, 2009Assignee: FormFactor, Inc.Inventor: Charles A. Miller
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Patent number: 7570314Abstract: There is provided a display device including a panel unit displaying an image, and a fixing member receiving the panel unit and including a bottom portion and a side portion extending from a boundary of the bottom portion toward the panel unit. The side portion of the fixing member includes at least two coupling areas and a support area extending from the coupling areas, wherein, a coupling opening is formed in the coupling areas, and the distance from one end of the coupling opening to the boundary of the bottom portion close to the other end of the coupling opening is smaller than the width of the support area.Type: GrantFiled: October 12, 2005Date of Patent: August 4, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Kyoung-Don Lee
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Patent number: 7569480Abstract: In a method of fabricating a semiconductor device, a first mask pattern is formed on a substrate. The first mask pattern has a first opening formed to expose the substrate. An oxidation barrier region is formed in the substrate exposed by the first opening, and the first mask pattern is patterned to form a second mask pattern having a second opening. A gate insulation layer is formed on the substrate exposed by the second opening. The gate insulation layer has a variable thickness.Type: GrantFiled: July 24, 2007Date of Patent: August 4, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Hua Liu, Jong-Hyon Ahn
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Patent number: 7566605Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.Type: GrantFiled: March 31, 2006Date of Patent: July 28, 2009Assignee: Intel CorporationInventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask
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Patent number: 7567076Abstract: The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms for inserting the board into an electrical contact in the oven for burn-in tests. Preferably, the cam mechanisms allow for extraction of a single board for inspection.Type: GrantFiled: March 25, 2008Date of Patent: July 28, 2009Assignee: Spansion LLCInventors: Wan Yen Teoh, Paiboon Subpanyadee, Kurt Joseph Perez, Chai Soon Teo, Swee Hin Ong
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Patent number: 7560293Abstract: The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs are manufactured as Lov resistance monitors in which mask alignment is misaligned with several ?m interval to perform a resistance measurement on each of the TEGs. Consequently, a resistance distribution corresponding to a tapered shape can be obtained in a channel forming region, a gate-overlapped region and a source/drain region.Type: GrantFiled: July 19, 2007Date of Patent: July 14, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Etsuko Asano, Osamu Nakamura, Masayuki Sakakura
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Patent number: 7560948Abstract: A new circuit for producing simulated electrostatic discharges (ESD) based on the Human Body Model (HBM) is disclosed for testing integrated circuits. HBM ESD test systems provide stress pulses defined by industry standards. The pulses produced by prior art have small imperfections or anomalies. These anomalies can cause incorrect testing to certain devices. The improved ESD HBM test system herein disclosed provides pulses meeting the requirements of industry standards while reducing several anomalies to negligible levels.Type: GrantFiled: January 11, 2007Date of Patent: July 14, 2009Assignee: Thermo Keytek LLCInventor: Evan Grund
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Patent number: 7562020Abstract: A wearable computer system has a user interface with at least an audio-only mode of operating, and that is natural in appearance and facilitates natural interactions with the system and the user's surroundings. The wearable computer system may retrieve information from the user's voice or surroundings using a passive user interface. The audio-only user interface for the wearable computer system may include two audio receivers and a single output device, such as a speaker, that provides audio data directly to the user. The two audio receivers may be miniature microphones that collaborate to input audio signals from the user's surroundings while also accurately inputting voice commands from the user. Additionally, the user may enter natural voice commands to the wearable computer system in a manner that blends in with the natural phrases and terminology spoken by the user.Type: GrantFiled: March 3, 2006Date of Patent: July 14, 2009Assignee: Accenture Global Services GmbHInventors: Dana Le, Lucian P. Hughes, Owen E. Richter
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Patent number: 7560940Abstract: A method and installation for analyzing an integrated circuit. The method includes, for a plurality of surface points of the integrated circuit, the following steps: applying a laser radiation, in one point of the surface of the integrated circuit; exciting the circuit; collecting the response of the circuit to the excitation; calculating the propagation time intervening between the excitation time and the response-collecting time; and creating an image of the integrated circuit showing a value representing the propagation time at each point of laser radiation application.Type: GrantFiled: September 30, 2005Date of Patent: July 14, 2009Assignee: Centre National d'Etudes SpatialesInventors: Romain Desplats, Kevin Sanchez, FĂ©lix Beaudoin
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Patent number: 7545015Abstract: A photodetection device is provided that includes a semiconductor substrate having a back surface which serves as a light-incident surface, and a front surface which opposes the back surface and is provided with a CCD reading part that detects light propagating from the back surface; a cooling device cooling the CCD reading part; and a package having a cavity that houses the semiconductor substrate and cooling device. The semiconductor substrate is fixed to a cavity bottom part of the package via the cooling device, and at the back surface thereof, a portion corresponding to a region at which the CCD reading part is disposed, is made thin. The cooling device has a cooling surface contacting the front surface of the semiconductor substrate while covering the region at which the CCD reading part is disposed.Type: GrantFiled: October 8, 2003Date of Patent: June 9, 2009Assignee: Hamamatsu Photonics K.K.Inventors: Hiroya Kobayashi, Masaharu Muramatsu
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Patent number: 7545136Abstract: A device for measuring current comprises a magnetic field sensor for measuring the magnetic field produced by a current I flowing through a current conductor and a yoke of a magnetic material with a relative permeability of at least 100. The magnetic field sensor preferably comprises a semiconductor chip with at least one Hall element and an electronic circuit for the operation of the Hall element. The yoke consists of an oblong piece of sheet metal or a laminate of sheet metals with two ends, that has been brought by bending into a form in which the front sides of the ends of the yoke face each other and are separated by an air gap. The ends of the yoke may be flush, tapered, or flayed relative to the width of the yoke.Type: GrantFiled: January 16, 2007Date of Patent: June 9, 2009Assignee: Melexis Technologies SAInventors: Robert Racz, Samuel Huber, Markus Gloor
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Patent number: 7544527Abstract: An optoelectronic assembly for an electronic system includes a thermally conductive, metallized transparent substrate having a first surface and an opposite second surface. A support chip set is bonded to the transparent substrate. A first substrate is in communication with the transparent substrate via the second surface and support chip set therebetween. A second substrate is in communication with the second surface of the first substrate and is configured for mounting at least one of data processing, data switching and data storage chips. An optoelectronic transducer is in signal communication with the support chip set, and an optical signaling medium having one end with an optical fiber array aligned with the transducer is substantially normal to the first surface of the transparent substrate. The support chip set and the transducer share a common thermal path for cooling.Type: GrantFiled: April 11, 2006Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Alan F. Benner, How Tzu Lin, Frank L. Pompeo, Subhash L. Shinde