Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

Abstract: A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.

Abstract: A material for forming a conductive structure for a micromechanical current-driven device is described, which is an alloy containing about 0.025% manganese and the remainder nickel. Data shows that the alloy possesses advantageous mechanical and electrical properties. In particular, the sheet resistance of the alloy is actually lower and more stable than the sheet resistance of the pure metal. Accordingly, when used for conductive leads in a photonic device, the leads using the NiMn alloy may provide current to heat the photonic device while generating less heat within the leads themselves, and a more stable output.

Abstract: A testing system contactor with an integral temperature measurement sensor.

Abstract: A vertical-type electric contactor connected to a bump of an electric contactor is provided. The vertical-type electric contactor includes a support beam, vertically bonded with the bump, in which at least two elastic parts are spaced apart from each other; a fixed part disposed at the bottom end of the support beam for fixing the support beam; and a tip part disposed at the bottom end of the fixed part, the tip part and the fixed part being a single body. According to the vertical-type electric contactor, a reaction force generated at a tip part is effectively distributed to test electric devices without damage of the vertical-type electric contactor.

Abstract: A semiconductor probe having an embossed resistive tip and a method of fabricating the semiconductor probe are provided. The semiconductor probe includes a protrusion portion protruded to a predetermined height on a cantilever in a first direction crossing a length direction of the cantilever, an embossed resistive tip formed on the protrusion portion, and first and second semiconductor electrode regions formed at opposite sides of the embossed resistive tip at the protrusion portion, wherein the cantilever is doped with a first dopant, the first and second semiconductor electrode regions and the embossed resistive tip are doped with a second dopant having a different polarity from the first dopant, and the embossed resistive tip is doped with a concentration lower than the first and second semiconductor electrode regions.

Abstract: A conductive connector includes a flexible-deflectable extension having a probing end and a head connection end. A conductive transmission path extends between the probing end and the head connection end. A pogo-rotational-action pin is electrically connected to the transmission path at the head connection end of the flexible-deflectable extension.

Abstract: There is provided a method of manufacturing a conductive layer of in a signal transmission substrate. The method includes sewing conductive thread in sheet-like material having an insulating property so as to form one of a plurality of low resistance regions using the conductive thread in a high resistance region formed by the sheet-like material, moving the conductive thread from an end point of a previously sewed low resistance region to a start point of a low resistance region to be sewed subsequently, repeating the sewing and moving steps to form the plurality of low resistance regions in the high resistance region, and forming a plurality of holes in the conductive layer by press working so that an electrical component attached to at least one of the plurality of holes is able to transmit a signal between neighboring ones of the plurality of low resistance regions.

Abstract: The invention is a method of producing an array, or multiple arrays of quantum dots. Single dots, as well as two or three-dimensional groupings may be created. The invention involves the transfer of quantum dots from a receptor site on a substrate where they are originally created to a separate substrate or layer, with a repetition of the process and a variation in the original pattern to create different structures.

Abstract: A method and apparatus for detecting defects includes irradiating and scanning an electron beam focused on an area of a sample, detecting charged particles generated from the sample by the irradiating and scanning of the electron beam with a first detector which detects charged particles having relatively low energy to obtain a first image of the area and with a second detector which detects charged particles having relatively high energy to obtain a second image of the area, comparing the first inspection image of the area with a first reference image to generate a first difference image, and comparing obtained second image of the area with a second reference image to generate a second difference image, and detecting an open defect or a short defect from at least one of the generated first difference image and the second difference image.

Abstract: A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test pattern data.

Abstract: A semiconductor device includes a substrate and a semiconductor layer formed on the substrate. The substrate has: a flat region provided in a main surface thereof; a first indentation region provided in a portion of the main surface different from the flat region and formed with first recesses; and a second indentation region provided between the first indentation region and the flat region, formed with second recesses, and having a lower probability of occurrence of growth nuclei than the first indentation region and a higher probability than the flat region in the case where a crystal of a semiconductor is grown on the main surface.

Abstract: An insert comprises an insert body having an IC housing part, a drive plate being allowed to move up and down attached to the insert body and a latch being allowed to swing attached to the insert body and having a pressing portion formed at its lower end portion. The latch swings along with the upward/downward move of the drive plate, and the pressing portion of the latch goes out to the IC housing part when the drive plate moves upward and presses an IC device housed in the IC housing part against a sidewall portion of the IC housing part.

Abstract: A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer.

Abstract: An apparatus for testing a semiconductor device that has opposing first and second sides is provided. The semiconductor device includes at least one functional unit on the first side and a plurality of terminals on the second side. The apparatus may include, but is not limited to, a mounting structure, and a plurality of electrodes. The mounting structure has at least one stage that is configured to allow the semiconductor device to be mounted thereon. The mounting structure has a communicating hole that penetrates the mounting structure from the stage. The communicating hole allows the at least one functional unit to face to the communicating hole while the semiconductor device is mounted on the stage. Each of the plurality of electrodes is configured to be contactable to a corresponding one of the plurality of terminals, while the semiconductor device is mounted on the stage.

Abstract: An electric current detector has a bus bar with a current direction changing section for changing a direction of electric current through the bus bar, and a magnetic detector disposed in the current direction changing section of the bus bar. The current direction changing section of the bus bar has a pair of parallel portions at which the bus bar is orthogonally deformed, and a connection portion at which the pair of parallel portions are connected, and the magnetic detector is disposed between the pair of parallel portions. The magnetic detector has a magnetic detection element disposed on a substrate, and a yoke surrounding the substrate and allowing the magnetic detection element to be placed between both ends thereof.

Abstract: A QFN integrated circuit is mounted on a leadframe having multiple lead lands and resin material encapsulates the integrated circuit leaving the lead lands exposed. Subsequently a sawing operation divides the lead lands into multiple leads, and the leadframe and resin material are partitioned to form packages. The pitch of the resultant leads is not limited by the pitch of the lead lands of the leadframe, so the leadframe can be of the relatively cheap generic leadframe variety, in which the pitch of the lead lands is higher than the desired pitch of the leads of the completed package. The sawing operation may further include reshaping the diepad area of the leadframe to produce heat sink fins, for improved heat dissipation. The proposed process is suitable both to produce packages including only a single integrated circuit, and also to produce multi-chip modules.

Abstract: A temperature detection function-incorporating current sensor includes a Hall IC, connector terminals for respectively outputting signals, detected by the Hall IC, to the exterior. The Hall IC includes a magnetism detection portion for detecting a magnitude of a magnetic field, a temperature detection portion for detecting an ambient temperature, and a temperature compensation portion for correcting an error of the magnetism detection portion due to temperature dependency based on the temperature detected by the temperature detection portion. The detection signal of the magnetism detection portion, corrected with respect to the error, and the temperature signal detected by the temperature detection portion are outputted via the connector terminals to the exterior. In this current sensor, it is not necessary to provide an additional temperature detection part, and also it is not necessary to effect an operation for connecting such a part to a board.

Abstract: An apparatus having a plurality of test units (520), a loading transport unit (510) transporting a plurality of electronic devices from a customer tray (4C) to a test tray (4T) before being loaded in a test unit, and a classifying transport unit (530) transporting a plurality of electronic devices from a test tray while classifying them to customer trays in accordance with test results, the loading transport unit being provided at least at a frontmost stage of a plurality of test units, the classifying transport unit being provided at least at a rearmost stage of the plurality of test units, the test tray being successively conveyed from the frontmost stage to the rearmost stage of the plurality of test units in the state carrying electronic devices and returned from the rearmost stage test unit to the frontmost stage test unit.

Abstract: A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic.