Abstract: Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: A storage system with privacy-centric multi-partitions and method for use therewith are provided. In one embodiment, a storage system comprises a memory configured to be partitioned into a plurality of partitions, wherein each partition is associated with its own boot block, and wherein each boot block is configured to boot any of the plurality of partitions. The storage system also comprises a controller configured to communicate with the memory and to: in response to a failure to boot one of the plurality of partitions with that partition's boot block, use a boot block of another one of the plurality of partitions to boot the one of the plurality of partitions; and restrict access to each of the plurality of partitions only to authenticated entities. Other embodiments are provided.

Abstract: This application describes a hardware accelerator, a computer system, and a method for accelerating Graph Neural Network (GNN) node attribute fetching. The hardware accelerator comprises a GNN attribute processor; and a first memory, wherein the GNN attribute processor is configured to: receive a graph node identifier; determine a target memory address within the first memory based on the graph node identifier; determine, based on the received graph node identifier, whether attribute data corresponding to the received graph node identifier is cached in the first memory at the target memory address; and in response to determining that the attribute data is not cached in the first memory: fetch the attribute data from a second memory, and write the fetched attribute data into the first memory at the target memory address.

Abstract: Systems and methods for cloud object storage and versioning are provided. In an example, a cloud object storage and versioning system (COSVS) coordinates insertion of metadata into a database and data into an object store in a compute infrastructure, the compute infrastructure including the database, the object store, a data source, and a client application interacting with the data source. The COSVS has an architecture comprising a client API layer confined to provide an interface to the client application to facilitate storing or restoring of items originally obtained from the data source, and query different versions of item content originally obtained from the data source; a deduplication layer to deduplicate item content and store items originally obtained from the data source devoid of external item metadata or semantic relations among items; and a packing layer confined to store and retrieve bytes of item or object content.

Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.

Abstract: The technology disclosed herein involves tracking contention and using the tracked contention to manage processor cache. The technology can be implemented in a processor's cache controlling logic and can enable the processor to track which locations in main memory are contentious. The technology can use the contentiousness of locations to determine where to store the data in cache and how to allocate and evict cache lines in the cache. In one example, the technology can store the data in a shared cache when the location is contentious and can bypass the shared cache and store the data in the private cache when the location is uncontentious. This may be advantageous because storing the data in shared cache can reduce or avoid having multiple copies in different private caches and can reduce the cache coherency overhead involved to keep copies in the private caches in sync.

Abstract: A storage system receives data to be stored in its memory. A controller in the storage system allocates a primary block of the memory to store the data and determines the health of the allocated block. If the controller determines that the allocated block is not healthy enough to reliably store the data, the controller allocates a secondary block to redundantly store the data.

Abstract: A storage system, and a method for operating a storage system. In some embodiments, the system includes a first storage device and a second storage device, and the method includes: determining that the first storage device is in a read-only state and that the second storage device is in a read-write state; performing a write operation, of a first stripe, to the storage system; performing a first read operation, of a second stripe, from the storage system; and performing a second read operation, of the first stripe, from the storage system, wherein: the performing of the write operation includes: writing a portion of the first stripe to the second storage device, and making an entry in a mapping table for the first stripe.

Abstract: The present disclosure describes a method to manage an enterprise data storage system, the method including: dividing storage disks of the enterprise data storage system into multiple virtual storage subsystems, wherein each virtual storage subsystem hosts a non-overlapping subset of the storage disks, and wherein each virtual storage subsystem includes a level-2 cache memory dedicated thereto; establishing a communication path between the level-2 cache memory dedicated to each virtual storage subsystem and a main cache of the enterprise-level data storage system; and maintaining a copy of transaction data from the non-overlapping subset of the storage disks hosted by each virtual storage subsystem in the level-2 cache memory dedicated thereto such that when the main cache searches for the copy of the transaction data, the main cache fetches, over the communication path, the copy of the transaction data from the level-2 cache memory of the virtual storage subsystem.

Abstract: A memory includes: a non-volatile memory suitable for storing a defect address; a register suitable for receiving and storing the defect address from the non-volatile memory during a boot-up operation, and receiving and storing an address that is input from an exterior during a register access operation; a comparison circuit suitable for comparing the address stored in the register with an address that is input from the exterior to produce a comparison result; redundant memory cells that are accessed according to the comparison result of the comparison circuit and a redundancy activation bit; and normal memory cells that are accessed according to the comparison result of the comparison circuit and the redundancy activation bit.

Abstract: A method, computer program product, and computing system for copying a storage protection configuration for one or more storage resources from a first storage array to at least a second storage array in a storage cluster. A communication failure between at least a pair of storage arrays may be detected, thus defining a surviving storage array and at least one failed storage array. The communication failure between the surviving storage array and the at least one failed storage array may be resolved. The storage protection configuration may be synchronized from the surviving storage array to the at least one failed storage array. The storage protection configuration for the one or more storage resources of each storage array of the at least a pair of storage arrays may be arbitrated.

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: receiving, by a host system, an indication that a storage capacity of a memory sub-system is affected by a failure, wherein the memory sub-system stores data of a storage structure and comprises memory cells storing multiple bits per cell; instructing, by the host system, the memory sub-system to operate at a reduced capacity, wherein the reduced capacity reduces the quantity of bits stored per memory cell; receiving, by the host system, an indication that the memory sub-system comprises data in excess of the reduced capacity; providing, by the host system, a storage location to the memory sub-system, wherein the storage location is external to the memory sub-system; and enabling the memory sub-system to store the data of the storage structure at the storage location.

Abstract: A sub-Non-Uniform Memory Access (sub-NUMA) clustering fault resilient memory system includes an initialization subsystem that is coupled to a processing system and a memory system. The initialization subsystem determines that the processing system and the memory system are configured to provide a plurality of NUMA nodes, allocates a respective portion of the memory system to each of the plurality of NUMA nodes, and configures each respective portion of the memory system to mirror a mirrored subset of that respective portion of the memory system. Subsequently, respective data that is utilized by each of the plurality of NUMA nodes provided by the processing system and the memory system and that is stored in the mirrored subset of the respective portion of the memory system allocated to that NUMA node is mirrored in that respective portion of the memory system.

Abstract: Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.

Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Abstract: The present disclosure generally relates to efficient execution of compare commands. Reads from the memory device for the compare commands are scheduled. Available chunks of data is received from the memory device, and the corresponding data is received from the host device. The data is compared. If the data does not match, the remaining reads are cancelled, and a compare completion is placed in the completion queue indicating a failed compare command. If all of the data matches, then a compare completion is placed in the completion queue indicating a successful compare command. Read transfers from the host device are scheduled based on availability of read data from the memory device side. By doing so, less buffers are needed to hold the data internally until both chunks of data are available. In so doing, synchronization between read data availability and retrieving data from the host device is synchronized.

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

Abstract: An arbiter gathers translation invalidation requests assigned to state machines of a lower-level cache into a set for joint handling in a processor core. The gathering includes selection of one of the set of gathered translation invalidation requests as an end-of-sequence (EOS) request. The arbiter issues to the processor core a sequence of the gathered translation invalidation requests terminating with the EOS request. Based on receipt of each of the gathered requests, the processor core invalidates any translation entries providing translation for the addresses specified by the translation invalidation requests and marks memory-referent requests dependent on the invalidated translation entries. Based on receipt of the EOS request and in response to all of the marked memory-referent requests draining from the processor core, the processor core issues a completion request to the lower-level cache indicating completion of servicing by the processor core of the set of gathered translation invalidation requests.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.