Patents Examined by Kaushikkumar M Patel
  • Patent number: 11531620
    Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: December 20, 2022
    Assignee: Arm Limited
    Inventors: Kishore Kumar Jagadeesha, Jamshed Jalal, Tushar P Ringe, Mark David Werkheiser, Premkishore Shivakumar, Lauren Elise Guckert
  • Patent number: 11531604
    Abstract: Methods, computer program products, computer systems, and the like are disclosed that provide for scalable deduplication in an efficient and effective manner. For example, such methods, computer program products, and computer systems can include determining whether a source data store and a replicated data store are unsynchronized and, in response to a determination that the source data store and the replicated data store are unsynchronized, performing a resynchronization operation. The source data stored in the source data store is replicated to replicated data in the replicated data store. The resynchronization operation resynchronizes the source data and the replicated data.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Veritas Technologies LLC
    Inventors: Rushikesh Patil, Sunil Hasbe
  • Patent number: 11520700
    Abstract: A holistic view of cache class of service (CLOS) to include an allocation of processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Malini K. Bhandaru, Iosif Gasparakis, Sunku Ranganath, Liyong Qiao, Rui Zang, Dakshina Ilangovan, Shaohe Feng, Edwin Verplanke, Priya Autee, Lin A. Yang
  • Patent number: 11513728
    Abstract: A storage device includes a main storage and a storage controller to control the main storage. The main storage stores data and includes a plurality of nonvolatile memory devices. The storage controller loads at least one of (a) at least a portion of mapping tables and (b) at least one of a portion of directories to a host memory buffer included in an external host device, based on at least one of a size of the host memory buffer and locality information associated with a data access pattern of the host device. The mapping tables are stored in the nonvolatile memory devices and the mapping tables indicate a mapping relationship between a physical address and a logical address of corresponding ones of the nonvolatile memory devices. The directories store address information of the mapping tables.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-Ryun Lee, Bum-Hee Lee
  • Patent number: 11494305
    Abstract: A linked list searching method and device are configured to search a linked list by using a cache memory. The method includes the operations of: writing the linked list in a memory; writing the data of a first node in a first row of a tag memory of the cache memory, and writing an address of the first node in a first row of a data memory of the cache memory; writing the data of a second node in a second row of the tag memory, and writing the address of the second node in a second row of the data memory; and searching the data of the second node in the tag memory to directly retrieve the address of the second node when searching the address of the second node in the linked list according to the data of the second node.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 8, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ju Lu
  • Patent number: 11487664
    Abstract: A technique performs data reduction on host data of a write request during ingest under certain circumstances. Therein, raw host data of a write request is placed from the host into a data cache. Further, a data reducing ingest operation is performed that reduces the raw host data from the data cache into reduced host data (e.g., via deduplication, compression, combinations thereof, etc.). After completion of the data reducing ingest operation, a late-binding operation is performed that updates a mapper with ability to access the reduced host data from secondary storage. Such ingest-time data reduction may be enabled/disabled (e.g., turned on or off) per input/output (I/O) operation (e.g., used only for relatively large asynchronous I/O operations) and/or activated in situations in which the ingest bandwidth is becoming a bottleneck.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 1, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vamsi K. Vankamamidi, Ronen Gazit
  • Patent number: 11487653
    Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Qing Liang
  • Patent number: 11467963
    Abstract: A method, computer program product, and computing system for receiving, at a node of a multi-node storage system, one or more updates to a reference count associated with a metadata block. One or more reference count deltas associated with the metadata block may be stored in a cache memory system of the node. An existing copy of the metadata block in a cache memory system of each other node of the multi-node storage system may be retained.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: October 11, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Bar David, Bar Harel, Dror Zalstein
  • Patent number: 11461234
    Abstract: A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 4, 2022
    Assignee: Numascale AS
    Inventors: Thibaut Palfer-Sollier, Einar Rustad, Steffen Persvold
  • Patent number: 11442858
    Abstract: Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dean Walker, Bryan D. Hornung, Tony M. Brewer, David M. Patrick, Christopher A. Baronne
  • Patent number: 11442637
    Abstract: A technique manages drive space within a storage system having a main data services environment configured to perform data storage operations on behalf of a set of hosts and a simple data services environment configured to load the main data services environment. The technique involves, while the simple data services environment is running on the storage system, using the simple data services environment to load the main data services environment on to the storage system. The technique further involves, after the main data services environment is loaded on to the storage system, providing a drive space communication from the simple data services environment to the main data services environment. The technique further involves receiving, by the simple data services environment, allocation of drive space from the main data services environment in response to the drive space communication.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: September 13, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Yuval Harduf, Peter J. McCann
  • Patent number: 11436154
    Abstract: A first group of physical blocks of a memory system is assigned to a first group of a plurality of logical blocks. A second group of physical blocks of the memory system are identified at a location is that is based on an offset and the first group of physical blocks. The second group of physical blocks of the memory system are assigned to a second group of the plurality of logical blocks. A third group of physical blocks of the memory system are identified at a location that is based on the offset and the second group of physical blocks. The offset is used to identify the location of the third group of physical blocks relative to the location of the second group of physical blocks. The third group of physical blocks of the memory system are assigned to a third group of the plurality of logical blocks. Data is stored by using a system block with the assigned first group, the assigned second group, and the assigned third group of physical blocks.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Karl D. Schuh
  • Patent number: 11429318
    Abstract: Techniques include receiving a backup request for backing up data on a production VVOL, to which is assigned physical space from storage devices in a first storage tier. When the production VVOL and a snapshot VVOL exist, and a write request is received to a data block on the production VVOL that is shared between the production VVOL and the snapshot VVOL, then the techniques include capturing a snapshot of the production VVOL by redirecting the write request to newly allocated space on the production VVOL, writing new data to the newly allocated space, and storing metadata referring to the original block(s) on the production VVOL. Based on an IO workload threshold, the techniques include copying, in a background process, the original version of the modified block from the production VVOL to a snapshot VVOL, to which is assigned physical storage space from storage devices in a second storage tier.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 30, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sergey Alexandrovich Alexeev, Alexey Vladimirovich Shusharin, Dmitry Tylik, Yakov Stanislavovich Belikov, Ekaterina Konstantinovna Sigalova
  • Patent number: 11416401
    Abstract: Embodiments of the disclosed technology relate to a memory system and an operating method thereof. According to the embodiments of the disclosed technology, the memory system may check N flag sets corresponding to N cache lines configured to cache map data,—Each flag set includes M flags, each flag indicating whether or not a cache hit for indicating a particular piece of data being stored in the map cache has been made for each of the M data units included in a corresponding cache line—may check target map data based on a number of flags indicating the cache hit for a corresponding data unit and included in the first flag set corresponding to the first cache line among the N cache lines.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11403022
    Abstract: In a storage system that implements RAID (D+P) protection groups a drive subset initially has (D+P) drives with (D+P) partitions. The drive subset is made to be symmetrical such that protection group members are symmetrically distributed in a matrix of drive rows and partition columns that represents the drive subset. A single new drive is added by partitioning the new drive with (D+P) partitions, moving existing protection group members from a selected partition of the (D+P) drives to partitions of the single new drive by rotating the selected partition by 90 degrees, and adding protection group members of a new protection group to the vacated selected partition of the (D+P) drives. The process is repeated until (D+P) new drives have been added in single drive increments. The resulting drive subset is then split by forming a non-symmetric drive subset from the (D+P) drives and forming a symmetric drive subset from the (D+P) new drives.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: August 2, 2022
    Assignee: Dell Products L.P.
    Inventors: Kuolin Hua, Kunxiu Gao
  • Patent number: 11379319
    Abstract: A storage system is connected to a backup storage system over a Storage Area Network (SAN). The backup storage system is managed by a backup server. The storage system includes a primary volume, a secondary volume configured to be mounted to a backup volume in the backup storage system and configured to be paired with the primary volume, and a processor configured to, for receipt of a backup operation request from the backup server, copy the primary volume to the secondary volume through a pair operation based on an Input/Output (I/O) between the storage system and a host computer managing the storage system, mount the secondary volume to the backup volume, and based on the I/O, copy the secondary volume to the backup volume through the SAN.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: July 5, 2022
    Assignee: HITACHI, LTD.
    Inventors: Yoshihiro Yoshii, Tomohiro Kawaguchi
  • Patent number: 11379121
    Abstract: An apparatus comprises at least one processing device configured to identify a protection operation to be performed for a virtual storage volume, the virtual storage volume comprising two or more storage volumes on two or more storage systems, a first one of the storage volumes on a first one of the storage systems comprising data that is mirrored on a second one of the storage volumes on a second one of the storage systems different than the first storage system. The processing device is also configured to monitor parameters characterizing operation of the storage systems, to generate a recommendation of a given one of the first and second storage volumes to back up to a third storage volume based on the monitored parameters characterizing operation of the storage systems, and to perform the protection operation for the virtual storage volume based on the generated recommendation.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 5, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sunil Kumar, Prashant Pokharna, Ashutosh Kumar Singh
  • Patent number: 11366759
    Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: June 21, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
  • Patent number: 11360688
    Abstract: In one aspect a data replication process in a storage system includes creating, at a first target site, an empty container in a storage system. The empty container matches a container at a source site in response to initiation of an asynchronous data replication process. An aspect also includes transmitting a command to a second target site to create a container at the second target site. The first target site performs the asynchronous data replication process, which includes scanning the data upon receipt from the source site for a first target replication cycle and transmitting the scanned data to the container at the second target site for a second target replication cycle.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 14, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: David Meiri, Anton Kucherov
  • Patent number: 11360891
    Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: June 14, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh