Abstract: A system and method for sanitizing a mass storage device on a host computer which includes a control system which receives input which starts a process of sanitizing a mass storage device, which includes a switch which isolates the mass storage device from an input interface that is used in normal operations and provides signals from an alternate input to the mass storage device to sanitize the mass storage.

Abstract: Direct memory access data path for RAID storage is disclosed, including: receiving, at a Redundant Array of Independent Disks (RAID) controller, a request to write data to be distributed among a plurality of storage devices; computing parity information based at least in part on the data associated with the request; causing the parity information to be stored on a first subset of the plurality of storage devices; and causing the data associated with the request to be stored on a second subset of the plurality of storage devices, wherein the plurality of storage devices is configured to obtain the data associated with the request directly from a memory that is remote to the RAID controller, and wherein the data associated with the request does not pass through the RAID controller.

Abstract: In at least one embodiment, processing can include acquiring a spinlock on a cached copy of a metadata (MD) page includes a field stored in two cache lines; updating a register to include an updated value of the field; determining whether a first portion of the updated value of the register is non-zero, wherein two portions of the updated value of the field as stored in the register correspond to the two cache lines; and responsive to determining that the first portion of the updated value of the register is non-zero, performing processing including: storing the first portion of the updated value of the field from the register in the first cache line; and subsequent to performing storing the first portion, storing the second portion of the updated value of the field as stored in the register in the second cache line.

Abstract: Nonvolatile data storage systems, methods, and devices are disclosed. In one example, a nonvolatile storage device includes a volatile memory, a controller electrically coupled to the volatile memory, a nonvolatile memory electrically coupled to the controller, and a backup power source electrically coupled to the controller, the volatile memory, and the nonvolatile memory. The controller is configured to read and write primary data from a primary host and mirrored data from a secondary host in the volatile memory. The backup power source is configured to store sufficient energy to power the nonvolatile storage device during a backup operation. The controller is configured to, in response to a backup signal, copy the primary data and the mirrored data stored in the volatile memory to the nonvolatile memory.

Abstract: A memory device is configured to communicate with one or more external devices, the memory device including a configurable bit or a mode select pin for determining which one of two or more different communication protocols that the memory device uses to communicate with the one or more external devices, wherein the two or more different communications protocols include at least a Controller Area Network (CAN) protocol and a System Management Bus (SMBus) protocol.

Abstract: A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address.

Abstract: Novel techniques are described for lock-free sharing of a circular buffer. Embodiments can provide shared, lock-free, constant-bitrate access by multiple consumer systems to a live stream of audiovisual information being recorded to a circular buffer by a producer. For example, when a producer system writes a data stream to the circular buffer, the producer system records shared metadata. When a consumer system desires to begin reading from the shared buffer at a particular time, the shared metadata is used to compute a predicted write pointer location and corresponding dirty region around the write pointer at the desired read time. A read pointer of the consumer system can be set to avoid the dirty region, thereby permitting read access to a stable region of the circular buffer without relying on a buffer lock.

Abstract: Application consistent dataset recovery using a cognitive control plane is provided. Sequence and timestamp of snapshots of volumes in a consistency group across heterogenous storage components corresponding to an application are recorded to facilitate operational recovery of application consistent datasets for the application. The cognitive control plane establishes a framework to manage, monitor, analyze, and update the consistency group and metadata to facilitate application consistent data recovery. A set of snapshots needed for the operational recovery of the application consistent datasets for the application is identified by mapping the sequence and timestamp of the snapshots of the volumes in the consistency group across the heterogenous storage components corresponding to the application in response to the computer determining that the operational recovery of the application consistent datasets for the application has been requested.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of the set of read commands; storing the first data in a first portion of a cache of the memory device; responsive to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands; responsive to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; transferring the first and second data to the controller.

Abstract: Techniques manage spare extents based on a dynamic window. In particular, in response to determining that the number of spare extents in a source storage device of a plurality of storage devices is lower than a predetermined threshold, a source extent is selected from the source storage device, and the source extent is an extent in a created stripe included in a storage system. Based on a set of extents other than the source extent in the stripe, a set of storage device sequences respectively associated with the set of extents are determined. A destination extent is identified from a plurality of spare extents in the set of storage device sequences. Data in the source extent is migrated to the destination extent. Accordingly, load balancing of the spare extents in each storage device of the storage system may be ensured.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: In a method disclosed for writing data, a device receives data, divides the data into one or more data fragments, obtains a first parity fragment based on the one or more data fragments and a second parity fragment of a written data fragment in a stripe distributed across a plurality of nodes, stores the one or more data fragments and the first parity fragment in the stripe.

Abstract: Systems and methods for performing application aware backups and/or generating other application aware secondary copies of virtual machines are described. For example, the systems and methods described herein may access a virtual machine, automatically discover various databases and/or applications (e.g., SQL, Exchange, Sharepoint, Oracle, and so on) running on the virtual machine, and perform data storage operations that generate a backup, or other secondary copy, of the virtual machine, as well as backups, or other secondary copies, of each of the discovered applications.

Abstract: Techniques disclosed herein provide techniques for coordinating host devices to synchronize data copy operations on storage arrays in an active-active storage configuration. For example, a method comprises managing generation of a backup copy of data in each of a set of storage arrays in an active-active storage configuration by causing one or more host devices that access the set of storage arrays to synchronously halt input-output operations associated with the set of storage arrays prior to causing the backup copy to be created in each of the set of storage arrays.

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.

Abstract: A position-measuring device includes a graduation carrier having a measuring graduation, position measurement electronics, a data memory and a power supply. The data memory includes a first memory which is a volatile memory for storing additional data, a second memory which is a writable non-volatile memory, and a memory controller for controlling transfer and storage of additional data from the first into the second memory. The power supply includes an input stage, a first output stage for the position measurement electronics, a second output stage for the data memory, and a voltage monitor which will turn off the first output stage of the power supply in response to a drop below a minimum value and signal the drop to the memory controller by a backup signal. In response to the backup signal, the memory controller will transfer additional data from the first memory into the second memory.