Abstract: In a method of making a flip-chip bonded GaAs-based opto-electronic device, removal of the GaAs substrate is facilitated by provision of a lattice matched (Al.sub.x Ga.sub.1-x)InP etch stop layer, exemplarily a Ga.sub.0.51 In.sub.0.49 P layer, and use of an etchant that isotropically etches GaAs such that an essentially mirror-like etch stop layer surface results, and that preferably exhibits an etch rate ratio of at least 200:1 for GaAs and the etch stop layer, respectively. Use of the novel substrate removal method can substantially increase device yield, and facilitate manufacture of large device arrays, e.g., arrays of detector/modulator diodes flip-chip bonded to Si CMOS chips.

Abstract: In accordance with the present invention, alternate lead-on-chip assembly methodologies have been developed which eliminate the use of a three layer film bonded to the leadframe, as currently employed in the art. According to the present invention, a dielectric paste is dispensed directly onto the top surface of the silicon die instead of the thermoplastic tape currently employed in the art. This approach required the development of apparatus and methods which meet the following requirements, e.g., 1) the method (and apparatus employed therefor) must provide comparable units/hour throughput to existing LOC assembly methods, and 2) the method must provide equivalent or superior package reliability when compared with tape bonded LOC packages. The invention method (and apparatus suitable for use therefor) satisfies these needs.

Abstract: An improved flip-chip bond connection and bonding method uses a "press fit" bond between a set of bond pad bumps or projections on a semiconductor chip and corresponding set of substrate bumps or projections on a substrate to self-align the chip with the substrate and enable flip-chips to be inexpensively bonded to substrates or packages with greater accuracy and a smaller pad pitch than previously achieved. In the method after normally one of the sets of bond pad bumps or substrate bumps has been cooled to shrink or contract so that the facing surfaces of each of the pad bumps and substrate bumps can be interdigitated, the chip and substrate are moved together so that the respective bumps are in a substantially common plane. The one cooled set of bumps is then warmed to expand that set of bumps sufficiently to form a lateral press-fit force between the facing surfaces, physically securing and electrically connecting the respective sets of bumps.

Abstract: Method for testing bare semiconductor die which includes providing a test substrate with a die receiving surface and bond pads with conductive traces which extend away from the surface and are connected to leads that may be contacted with test probes. A vacuum source is applied to an aperture in the die receiving surface. Atmospheric pressure holds the die in place during the connection of thin wires. After connection, the die is held in place during testing by the thin wires.

Abstract: A method of fabricating an integrated circuit device with a substantially uniform inter-layer dielectric layer. The method includes steps of providing a partially completed semiconductor wafer (400) where the partially completed semiconductor device has a first polysilicon layer (401) thereon. The method includes depositing a dielectric layer (405) overlying the polysilicon layer and portions of the partially completed semiconductor device at a pressure of about 1 atmosphere. A step of forming a second polysilicon layer overlying portions of the dielectric layer is also included. The dielectric layer depositing step includes combining an organic silane and an ozone at a concentration of 200 g/m.sup.3 and less.

Abstract: A semiconductor package with solder balls and a method for producing the package are disclosed. The package has no outer lead but is provided with the solder balls formed on the mold resin body, thus to allow a plurality of packages to be easily vertically layered when enlarging the memory capacity. The package producing method forms the solder balls through screen printing or dotting, or electroplating and vacuum depositing of solder paste, thus to need no typical forming step and to achieve the thinness of the package. A plurality of holes are provided in at least one of the top section and the bottom section of the mold resin body such that the holes communicate with the inner leads respectively. The solder balls are formed on the holes under the condition that a plurality of conductors are charged in the holes. The solder balls are electrically connected to the inner leads through the conductors.

Abstract: An ultra high-density integrated circuit module which includes a plurality of individual high-density integrated circuit packages. A plurality of the ultra high-density integrated circuit memory modules may be combined to form an ultra high-density memory bank for use in computers, or other applications requiring high-density on-board memory. The high-density integrated circuit packages which form the modules each have an internal lead frame and optional internal member which overlie an integrated circuit die. A thin, warp-resistant metal layer and an external heat conductor element are mounted to the exterior of the package. Heat is dissipated from the package while structural forces are selectively balanced.

Abstract: A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.

Abstract: A DIP integrated circuit package is disclosed which includes a trench-type DRAM and an associated non-symmetric lead frame having one or more Y-shaped leads which branch in the direction of die I/O pads. Such non-symmetric lead frames allow multiple use of pin spacing (i.e., one pin may be used to connect to widely spaced I/O pads on the DRAM die). Further, such structures serve to dissipate the generated heat, and thereby reduce noise, in high density trench-type DRAMs, such as 64 Mbit DRAMs. The lead frame is provided as a DIP lead frame which has no die attach pad and is wire bonded to I/O pads of the integrated circuit that are provided along a center line on the chip.

Abstract: A semiconductor device with a force and/or acceleration sensor (12), which has a spring-mass system (14, 16) responsive to the respective quantity to be measured and whose mass (16) bears via at least one resilient support element (14) on a semiconductor substrate (20). The semiconductor substrate (20) and the spring-mass system (14, 16) are integral components of a monocrystalline semiconductor crystal (10) with a IC-compatible structure. The three-dimensional structural form of the spring-mass system (12) is produced by anisotropic semiconductor etching, defined P/N junctions of the semiconductor layer arrangement functioning as etch stop means in order to more particularly create a gap (22) permitting respective movement of the mass (16) between the mass (16) and the semiconductor substrate (20).

Abstract: A chip carrier semiconductor device comprises a semiconductor chip having a surface on which a plurality of contact pads, a tape carrier overlying the semiconductor chip and a plurality of leads provided on the tape carrier to overly the semiconductor chip, each of the leads having an inside end being provided with at last one bump for bonding a board, the bump being positioned on an inside area of the contact pads.

Abstract: An element including a polycide electrode is formed on a silicon substrate, and after a BPSG film is deposited as an interlevel insulating film and a contact hole is formed therein, the substrate is lamp annealed in an atmosphere containing oxygen to reflow the BPSG film. After an HF process, an Al wiring is formed on the BPSG film, contacting the polycide electrode via the contact hole. It is possible to prevent an increase in the contact resistance of the polycide electrode.

Abstract: A method is disclosed for making a non-metallurgical connection between an integrated circuit (16) and either a circuit board (12) or second integrated circuit. In one embodiment, an electrical connection is formed between terminals (28) of an integrated circuit (16) and pads (20) on a circuit board (12) without metallurgically connecting the terminals (28) and pads (20). The integrated circuit (16) can be in either packaged or die form. A clamping mechanism (18, 36) attached to the circuit board (12) clamps the integrated circuit (16) to the circuit board (12).

Abstract: A method of making a microelectronic assembly includes bonding a plurality of lead connection sections arranged in a row to contacts of a microelectronic element such as a semiconductor chip having contacts in rows at the periphery of the chip. The leads have terminal sections secured to a dielectric support structure, and horizontally curved sections between the terminal regions and bond regions. After bonding, the dielectric support structure is lifted upwardly relative to the chip, so as to bend the leads into a vertically-extensive orientation. Partial straightening of the original horizontal curvature allows each lead to stretch and accommodate the vertical movement.

Abstract: A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).

Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Abstract: A new method and device to encapsulate integrated circuits such as flip chips and BGA packages. A special mold to surrounds the chip to be encapsulated in a cavity, and the encapsulant is injected into the cavity at an elevated pressure, and possibly at an elevated temperature. This shortens the cavity filling time by two or three orders of magnitude, compared to the conventional dispensing process. The reliability of the package is increased by increasing the adhesion of encapsulant to the package, by controlling fillet shape through in-mold curing, and by completely filling the cavity through proper mold design and, optionally, evacuation of the cavity prior to injection. The invention also allows the use of a wider range of encapsulants, including highly viscous material, fast curing materials and reworkable materials.

Abstract: An electronic device, particularly a solar cell, comprising a layer (16) of amorphous silicon (a-Si) and at least two layered electrodes (14, 18) each having an interface (20, 22) bordering said a-Si layer, in which at least one of the electrodes (14) is provided with pattern elements (14a) forming a preferably periodic micropattern. The average spacing of the pattern elements is preferably in the order of magnitude of the charge carrier drift lengths and is generally smaller than 1 .mu.m, particularly 50 to 500 nm. The micropattern is produced preferably by the effect of a laser beam interference pattern.

Abstract: A multi-layered structure and process for forming it arc described, incorporating a single crystal substrate, a plurality of epitaxial layers having graded composition wherein the layers have changing lattice spacings not exceeding about 2 percent per 1000 .ANG. of thickness whereby misfit dislocations are formed to relieve strain and then move to the edges of respective layers. The invention overcomes the problem of large numbers of misfit dislocations threading to the surface of the top layer, especially during device processing at temperatures in a range from 700 to 900 degrees Celsius. Fully relaxed, incommensurate structures having low defect densities are obtained, where arbitrary combinations of materials can be used.

Abstract: A heat sink-integrated semiconductor package is fabricated by a characteristic method comprising the steps of dispensing a liquid epoxy resin over at least the bare surface of a heat sink mounted with a semiconductor chip, curing said dispensed liquid epoxy resin to form a first encapsulating part so as to prevent delamination at the interface between said heat sink and said semiconductor chip, molding a mold compound to form a second encapsulating part to protect said package from the external environment. The semiconductor package of the present invention, the first encapsulating part is of stronger bonding strength than the second encapsulating part, so that the delamination phenomenon at the interface between heat sink and semiconductor chip can be prevented or relieved efficiently.