Abstract: A single semiconductor chip containing a control portion and a power portion including a power element associated with the control portion and a concave portion formed between the control portion and the power portion is mounted on a die pad so as to separate the control portion and the power portion. The die pad has a convex portion which is received in the concave portion and the semiconductor chip is divided to separate the control portion and the power portion by applying pressure to the chip or by applying laser beams, and the separated semiconductor chip portions are simultaneously bonded to the die pad.

Abstract: The device has a semiconductor die (18) mounted upon a downset X-shape die support (12) of a lead frame (10, 40). The lead frame also has tie bars (16) which are connected to the X-shape die support. Attached to the tie bars are thermal bars (14, 14') which are located between the semiconductor die and inner portion of the leads (20). The inner portion of the leads, the tie bars, and the thermal bars are offset from the plane occupied by the X-shape die support. The thermal bars aid in dissipating the heat from the die into the nearby lead tips so that the heat can be conducted out of the package body (30) through the thermally conductive lead frame. The semiconductor die is wire bonded to the inner portion of the leads. A package body (30) protects the die, the wire bonds (26), the thermal bars, and the inner portion of the leads.

Abstract: The process for forming a layer of metal silicide over polysilicon structures, such as gates and interconnect lines, is simplified by forming a layer of insulation material over the polysilicon structures, removing the layer of insulation material until the layer of insulation material is substantially planar and the thickness of the insulation material over the polysilicon structures is within a predetermined thickness range, etching the planarized layer of insulation material until portions of the polysilicon structures are exposed, depositing a layer of metal over the resulting structure, and then reacting the metal layer with the polysilicon structures to form the layer of metal silicide.

Abstract: A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are formed through the interconnect opening to establish electrical communication between the bond pads on the die and the conductors on the package body. The conductors on the package body can include solder bumps to permit the package to be flip chip mounted to a supporting substrate such as a printed circuit board or to be mounted in a chip-on-board configuration. The package can be fabricated by bulk micro-machining silicon wafers to form the package bodies, attaching the dice to the package bodies, and then singulating the wafer. Alternately the package body can be formed of a FR-4 material. In addition, multiple dice can be attached to a package body to form a multi-chip module.

Abstract: A manufacturing system for individually processing semiconductor wafers through a plurality of processing stations. The system has a plurality of processing stations, a multilevel track system that interfaces with the processing stations, and guided transport vehicles that operate on the track system to move individual wafers in wafer carriers between the stations. The carriers have a storage memory that contains the required process sequence and the capability to remember the completed process steps.

Abstract: A method of making a multi-chip module by thinning individual integrated circuit die or an integrated circuit wafer containing multiple integrated circuits; bonding thinned dice or a thinned wafer to a mylar, polyimide, semiconductor, or ceramic substrate; depositing at least one interconnect material over the wafer, where the first interconnect layer is deposited directly over the wafer; depositing a dielectric layer over each of the interconnect layers; opening vias in the dielectric layers in order to interconnect the dice and multi-chip module as required; and removing the substrate to form a thin, conformal, and high-yielding multi-chip module.

Abstract: A method for selectively depositing WSi.sub.x is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein WSi.sub.x is to be deposited overlying a first portion of the substrate and wherein WSi.sub.x is not to be deposited overlying a second portion of the substrate. A layer of organic material is provided over the surface of the substrate overlying the second portion of the substrate. A layer of WSi.sub.x is deposited over the surface of the substrate wherein the WSi.sub.x is deposited overlying the first portion of the substrate and wherein the presence of the organic material layer prevents the WSi.sub.x from depositing overlying the second portion of the substrate completing the selective WSi.sub.x deposition in the fabrication of an integrated circuit device.

Abstract: A semiconductor device having an Au electrode is fabricated as follows. As a first step, an insulating film is formed on a semiconductor substrate. As a second step, a contact hole is selectively formed in the insulating film to expose a part of the substrate. As a third step, a barrier metal layer is formed on an entire surface of a resultant structure to bury at least a part of the contact hole and form a barrier metal layer on the insulating film. As a fourth step, an Au layer is selectively formed on the barrier metal layer. As a fifth step, reactive dry etching is performed using the Au layer as a mask and using an etching gas, obtained by adding an O.sub.2 gas to a mixed gas of at least one type of chlorine based gas selected from a group of a chlorine gas and a carbon chloride gas, and at least one type of fluorine based gas selected from a group of a carbon fluoride gas and a carbon hydrogen fluoride gas in such a manner that a flow rate ratio of (O.sub.

Abstract: A method for forming a conductive vias in a non-conductive substrate having a through-hole formed therein intermediate two side thereof. The method utilizes the steps of: applying gold paste to the through-hole so as to provide electrical conduction therethrough; and under firing the gold paste when a thin conductive film is present upon the substrate and fully firing the gold paste when no thin conductive film is present on the substrate. Under firing the gold paste when a thin-film is present upon the substrate prevents degradation of the thin conductive film. Subsequent processing of the gold paste assures the integrity and reliability thereof. Thus, the gold paste provides enhanced conductivity and improved reliability, as compared to contemporary thin-film vias.