Abstract: The invention relates to a method and an apparatus for forming bonding bumps on wafers (5) to be plated in an electroless process (not requiring an externally applied voltage). According to the method, the object to be plated is immersed in a vessel (2) containing a desired solution (10) of metal salts thermostatted at a desired temperature. According to the invention, the wafer (5) to be plated is fixed to a filler block (4) which has a volume essentially equal to the volume of the process vessel (2) to the end of reducing the required filling volume of the vessel (2), and said filler block (4) is moved in the vessel (2) for improving the mixing of the solution of metal salts contained therein.

Abstract: A method for forming an upper metal wiring which is in contact with an under conductive layer in a highly integrated semiconductor device. The method includes the steps of forming a metal wiring layer on a lower insulating film, forming a contact hole in the insulating film to expose an under conductive layer, and growing a metal layer in the contact hole to fill up the contact hole, so that the metal wiring layer can be in contact with the lower conductive layer.

Abstract: A method of making an assembly package having an airtight cavity for housing an electrical element, such as a semiconductor chip. The method includes bonding a shell to a conductive base with a thermally setting alpha-staged epoxy resin which is characterized as being a gel in the uncured state at room temperature. The use of the alpha-staged epoxy resin, in contrast with the conventional beta-staged epoxy resin, results in an airtight cavity being formed without punctures or fissures in the epoxy resin. The method also provides a two-step heating process whereby the epoxy resin is cured at a first elevated temperature in the open atmosphere and further cured and stabilized at a second elevated temperature in a closed environment.

Abstract: According to a method of manufacturing a semiconductor package of the present invention, a plurality of leads and a large number of minute convex portions are respectively formed by plating on a surface of a metal base and in an outer peripheral area of the leads thereon. An insulative film for holding each of the leads is formed. A solder resist film is formed selectively on a portion including the outer peripheral area having the minute convex portions thereon. A projecting electrode is formed on an outer lead portion of each of the leads through an opening of the solder resist film on an outer lead portion of each of the leads. The metal base is selectively removed except a joint portion thereof on an outer periphery to separate the respective leads. Inner lead portions of the leads and a semiconductor chip are jointed together. The joint portion of the metal base is cut off.

Abstract: A method of fabricating a multi-chip package including an aluminum silicon substrate with an aluminum nitride layer thereon forming an electrically insulated surface and aluminum heat conductive areas positioned on the insulated surface. Conductors on the surface of the substrate defining mounting areas and external connections with each mounting area positioned adjacent an associated one of the heat conductive areas and a semiconductor chip mounted in each mounting area. Heat conductive elements connected to the rear surface of each chip and to the associated one of the plurality of heat conductive areas, and each chip encapsulated with reworkable encapsulant.

Abstract: A II-VI group compound semiconductor device having a p-type Zn.sub.x Mg.sub.1-x S.sub.y Se.sub.1-y (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) semiconductor layer, on which an electrode layer is formed with at least metallic nitride layer lying between the semiconductor layer and the electrode layer.

Abstract: A semiconductor package has a wiring circuit containing a conductive terminal formed on a first face of a substrate and a flat external connecting terminal electrically connected to the wiring circuit formed on a second face. An electrode pad is formed on a first face of a semiconductor chip. This semiconductor chip is mounted on the substrate with its first face down to oppose the first face of the substrate. A ball bump as a protruded electrode formed on the conductive terminal of the substrate and a ball bump as a protruded electrode formed on the electrode pad of the semiconductor chip are connected by solid phase diffusion. And, a sealing resin layer is formed in the space between the substrate and the semiconductor chip opposed to each other with a second face of the semiconductor chip exposed.

Abstract: A temporary package for testing semiconductor dice, a method for forming the temporary package and a method for testing dice using the temporary package are provided. The temporary package includes hard-metal ball contacts arranged in a dense grid pattern, such as a ball grid array. The dense grid pattern allows the temporary package to include a large number of ball contacts (e.g., 50 to 1000 or more) to permit testing of dice having a large number of bond pads, or dice that require a large number of input/output signals. The ball contacts can be formed of a metal such as nickel, copper or beryllium copper and are adapted to resist wear, deformation and breakage during continued use of the package. For forming the package, a package base can be formed with land pads and the ball contacts can be attached to the land pads by soldering, brazing, welding, or with a conductive adhesive.

Abstract: A semiconductor device according to the present invention includes a substrate made of an electrically insulative material having a relatively high thermal conductivity, a metallic pattern member provided on one major surface of the substrate and having an external terminal portion extending from the substrate, a semiconductor element mounted on the metallic pattern member, a metallic layer provided on the other major surface of the substrate, a heat dissipation plate fixed onto the metallic layer, and a mold body for coating both the substrate mounted with the semiconductor element and the heat dissipation plate so as to expose the external terminal portion.

Abstract: The present invention relates to a method for forming cobalt disilicide structure on a silicon substrate comprising the steps of depositing a cobalt layer on the substrate, thereafter depositing a refractory metal on the cobalt layer, thereby forming a bilayer structure on the said substrate, and heating the bilayer structure. The present invention also relates to a method for forming self-aligned cobalt disilicide on a metal oxide semiconductor transistor with a source drain and gate regions in a silicon substrate comprising the steps of: depositing a cobalt layer on the substrate, thereafter depositing a refractory metal layer on the cobalt layer, heating the silicon substrate, thereby forming a cobalt dislicide layer on the gate, source, and drain regions of the MOS transistor, and selectively etching the remaining nonsilicide cobalt and refractory metal from the substrate except from the source, drain, and gate regions.

Abstract: An improved salicide process for selectively forming a monocobalt disilicide film on a substrate having a surface including both an insulation region containing silicon and a silicon region comprises the following steps. Cobalt is deposited on the substrate, wherein the substrate is heated up and maintained at a first temperature which is capable of causing cobalt to react only with silicon in the silicon region without reacting with silicon in the insulation region. The substrate is subjected to a vacuum annealing at a temperature equal to or near the first temperature to form a film made of one selected from the group consisting of dicobalt monosilicide and monocobalt monosilicide.

Abstract: A plurality of connecting leads, each consisting of an internal lead and an external lead, are provided so as to extend inward from a lead frame main body, and are then cut off the lead frame main body. The connecting leads are electrically connected with an aluminum electrode of the semiconductor chip. A plurality of fixing leads, each having a distal end bent toward the semiconductor, are provided so as to extend inward from the lead frame main body and thereafter are cut off the lead frame main body. The semiconductor chip is clamped by the distal ends of the fixing leads. The semiconductor chip, the plural connecting leads and the plural fixing leads are sealed together into a resin package.

Abstract: A leadframe has conductive fingers with an insulating film located on a first portion of the fingers. The insulating film has openings into which contact pads formed of a noble metal are provided. Pads on a chip are wire bonded to these contact pads on the leadframe. The first portion is encapsulated in a molded package. The structure inhibits silver migration, provides insulation between wires and leadframe, and provides improved adhesion between plastic package and leadframe. A single insulating film with openings for providing the contact pads provides all these features.

Abstract: An IC carrier on which an integrated circuit (IC) package is loaded when electric testing of the IC package is carried out is described. The present invention enables an IC package to be loaded on or unloaded from the IC carrier smoothly without bending any of closely arranged fine leads, and prevents the lead from being deformed by falling impact when it is dropped. According to the present invention, an IC carrier for an IC package having an array of leads comprises an array of socket means for mating with the array of leads, wherein selected one of said socket means differs in an inner dimension from the other ones in the same array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

Abstract: A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.

Abstract: A packaged LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. Reduced-size filler particles are used in the encapsulant with the maximum allowable diameter of any particle depending upon the gap width between the lead frame and the die surface. Specifically, the maximum particle diameter is limited such that the ratio of maximum particle diameter to gap width is 0.95 or less, or preferably approximately 0.75. The reduced-size particles do not lodge between the leads and the active surface of the die during transfer molding of the encapsulant, thus, reducing point stresses on the active surface of the die by the filler particles.

Abstract: The disclosure relates to spot-facing for exposing an inner-layer conductor embedded in an insulator of a printed circuit board. The spot-facing removes the entire insulator by a mechanical cutter, except a part thereof, to a position just above the inner-layer conductor. The part of the insulator is smaller in thickness than the insulator removed by the mechanical cutter. Then, the remaining part of the insulator is removed by scanning the part with a laser beam to expose the inner-layer conductor. The laser beam is in a slender shape almost perpendicular to the scanning direction of the laser beam and has an almost uniform energy density along the slender shape. Cutter processing is sufficient to be done before the inner-layer conductor, and there is no fear of damaging the inner-layer conductor. Moreover, laser-beam processing is easy to control thermal influence on the portion to be processed of the circuit board, because the energy density of the laser beam is almost uniform.

Abstract: The invention relates to a method of manufacturing a semiconductor device (1) for surface mounting. Such a method is known, whereby such a semiconductor device is manufactured in that a semiconductor body with a semiconductor element is mounted on a metal lead frame with metal package leads, after which contact surfaces of the semiconductor element are connected to the package leads by means of bonding wires. It is found that semiconductor devices of small dimensions are difficult to realize by this known method, while in addition the manufacture of integrated circuits with very many package leads is comparatively expensive owing to the many connections which are to be made between the integrated circuits and the package leads. According to the invention, the semiconductor devices are packaged while they are still on a slice of semiconductor material, while the package leads are formed from the semiconductor material.

Abstract: In a method of sealing electronic parts with molded resin, a hollow sealing member is arranged on a mold surface of an upper mold section of a mold comprising the upper mold section and a lower mold section, so that the hollow sealing member is pressurized and expanded to convexly project from the mold surface of the upper mold section. In this state, the lower mold section is upwardly moved to be brought into contact with the expanded hollow sealing member. Further, an internal space portion, including pots, cull portions, resin passages and cavities, which is enclosed with the expanded hollow sealing member is set in a state isolated from the exterior when the upper mold section and the lower mold section are closed, so that the internal space portion is forcibly evacuated in this state. Thus, air, moisture and gases are efficiently and reliably suction-discharged from the internal space portion, whereby the internal space portion is set at a prescribed degree of vacuum.

Abstract: A method of planarizing an interlayer dielectric layer in a semiconductor integrated circuit device is provided, which method can remove remaining parts of the dielectric layer without removing the surface of the layer itself at a high throughput. After an insulating layer is formed on a chief surface of the semiconductor substructure, an interconnection layer having interconnection lines is formed on the insulating layer. An interlayer dielectric layer is formed on the insulating layer so as to cover the interconnection layer. The dielectric layer has steps or protrusions at positions corresponding to the underlying interconnection lines of the interconnection layer. Next, a patterned resist film is formed on the interlayer dielectric layer so as to have an inverted geometric shape relative to that of the interconnection layer. Then, using the patterned resist film as a mask, the interlayer dielectric layer is selectively etched to thereby partially remove the top of the protrusions by a predetermined depth.