Abstract: A process for forming a refractory metal thin film on a substrate by subjecting a gaseous mixture containing a halide of a refractory metal and the hydrogen gas to a plasma chemical vapor deposition, comprising the step of adjusting a mixing ratio of the halide of the refractory metal to the hydrogen gas to a relatively small value at an initial stage of the process and, subsequent to the initial stage of the process, adjusting the mixing ratio of the halide of the refractory metal to the hydrogen gas to a relatively large value.

Abstract: The semiconductor image sensor device of the multiple chip mount type is constructed such that electrical and mechanical connections are carried out concurrently among chips. Coupling chips 4 are utilized to couple a plurality of semiconductor image sensor chips 1 with each other, and the couple one semiconductor image sensor chip 1 to a driver substrate 3 which mounts thereon a semiconductor driving chip 2 for driving the semiconductor image sensor chips 1.

Abstract: A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package.

Abstract: A method for making a substrate for a semiconductor package comprising forming a conductive layer having a desired circuit pattern on the substrate; curing the conductive layer; and coining the cured conductive layer to make its surface uniform. The cured conductive layer may be plated with Ni, and subsequently with Au, and shaped to form a Au-plated board.

Abstract: The present invention relates to an improved method for forming a UBM pads and solder bump connections for flip chip which eliminates at least one mask step required in standard UBM pad forming processes. The method also includes repatterning bond pad locations.

Abstract: In a method for mounting an integrated optical component, a starting base structure includes a silica lower confinement layer and the cores of the future optical waveguides. This basic structure includes an alignment abutment so that a component to be mounted can be subsequently aligned with these waveguides. A silicon barrier layer is deposited on the abutment. Flame hydrolysis deposition is then used to deposit an upper silica layer to constitute the upper confinement layer of the waveguides. This silica layer also covers the alignment abutment, however. For this reason the region of the abutment is then etched by reactive ion etching to expose the abutment, which is protected from this etching by the barrier layer. The component to be mounted is then located relative to the abutment.

Abstract: A variety of lead configurations for use in packaged semiconductors, the leads including integral finger locking mechanisms to prevent leads from pulling out of an encapsulated package, and their method of manufacture. Each finger is comprised of a bent portion of the lead and has a length of approximately two to four times the thickness of the lead body. A finger may be integrally located at the lead tip or, where the lead includes one or more tabs, a finger may extend from any number of the tab edges. Any number of leads within a semiconductor package may incorporate a finger, and each lead may incorporate a plurality of fingers. A method of manufacturing the finger locking mechanism of the current invention includes forming a lead frame in a conductive strip, wherein the lead tips are separated from the die attach pad, so as to retain a sufficient length of each lead in appropriate locations to accommodate the formation of fingers by bending.

Abstract: An apparatus for processing an integrated circuit device comprises at least one insert having at least one beveled hole therein, the insert adapted to receive at least one semiconductor device. The apparatus further includes a tray having a pocket for receiving the insert and a slot, a deformable segment on the insert, and at least three posts on the insert. Further included is at least one tab on the deformable segment with one of the slots receiving the tab.

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.

Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

Abstract: A flip-chip semiconductor device (70) is formed by mounting a semiconductor die (20) to a wiring substrate (30). The wiring substrate includes a hole (39). An underfill encapsulation material (52) is dispensed around an entire perimeter of the semiconductor die. The underfill encapsulation material then flows toward the center of the die, expelling any trapped air through hole (39) of the wiring substrate to avoid voiding. By providing a method which utilizes an entire perimeter dispense, manufacturing time of the underfilling step is significantly reduced. At the same time, a uniform fillet is formed and the formation of voids in the underfill encapsulation material is avoided due to the presence of hole (39) in the wiring substrate. Multiple die (100) can also be underfilled using a single dispensing operation in accordance with the invention.

Abstract: A method of locating a socket on a printed circuit board which includes the steps of fabricating a plurality of pads and one or more fiducials on the upper surface of the printed circuit board, optically aligning a drill with the fiducial, and then drilling a socket hole through the printed circuit board at the location defined by the fiducial. A peg of the socket is inserted into the socket hole to align the socket with the printed circuit board. Alternatively, a method for locating holes on a printed circuit board includes the steps of forming a master tooling hole through the printed circuit board, locating a fiducial on the printed circuit board using the master tooling hole as a guide, focusing on the fiducial with an optically alignable drill, thereby aligning the drill, and then drilling a hole through the printed circuit board using the aligned drill.

Abstract: A method for manufacturing a semiconductor package, including providing a lead frame in which die pad and side rail areas of the lead frame are mechanically interconnected to, and electrically isolated from each other so that the exposed bottom surface of the die pad does not become coated with a metal plating film during surface treatment for coating outer leads of the lead frame.

Abstract: A hermetically packaged radiation imager includes a moisture barrier cover disposed over the imaging array and a hermetic seal structure disposed around the periphery of the moisture barrier cover to seal the cover to the underlying substrate. The hermetic seal structure comprises a solder seal disposed in contact with the moisture barrier cover and a dielectric material layer disposed between the solder seal and conductive lines extending from the imager array across the substrate surface. The hermetic seal structure further includes a primer layer that is disposed between the dielectric material layer and the solder seal to provide a foundation to which the solder seal adheres. The dielectric material layer is deposited in an atomic layer epitaxy technique, thus providing a thin layer having high structural integrity.

Abstract: An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit.

Abstract: A metal ring frame, having co-fired ceramic inserts, is hermetically sealed to a copper/molybdenum base using a brazing alloy having a melting temperature which is approximately the cross-over temperature for the TCE curves of the base and ring frame. Preferably the base contains at least 20% copper by weight. The brazing alloy is a silver/copper alloy such as 56% Ag, 22% Cu, 17% Zn and 5% Sn, or one with a higher brazing temperature such as 78/22 Ag/Cu, and is used for brazing both the inserts into the frame and the frame onto the base.

Abstract: A semiconductor processing method forms etch stop layers over semiconductor structures without the need for additional etching, masking, and deposition steps. A refractory metal capable of forming silicides and oxides under standard processing conditions is deposited over the deposition, oxide, and polysilicon layers of a MOS integrated circuit wafer. The coated wafer is first annealed to form refractory metal silicide layers over the unoxidized silicon structures. The coated wafer is then oxidized to convert unreacted refractory metal over the oxidized silicon structures into refractory metal oxide etch stops over these structures.

Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.

Abstract: Semiconductor structures and associated methods for limiting electromigration at wiring interfaces. Increased cross-sectional contact sections are employed, with conducting studs in contact therewith. Methods for fabrication and use are disclosed. Contacts for stackable integrated circuit chips and three-dimensional electronic modules particularly are modified with the disclosed structures and methods.

Abstract: A composite semiconductor device having a plurality of semiconductor chips (12, 13), a package (11) receiving the semiconductor chips (12, 13) and leads (14, 14', 15, 15') which are connected to electrode pads (17, 19) of the semiconductor chips (12, 13) and extend outside the package (11) is manufactured by a process comprising a first step for electrically connecting the electrode pads (17, 19) to the inner portion of the leads (14, 14', 15, 15') and packaging the semiconductor chips (12, 13) and the inner portion of the lead (14, 14', 15, 15') within the package (11), and a second step for connecting the lead (14') connected to the electrode pad (17) of the semiconductor chip (12) to the lead (15') connected to the electrode pad (19) of the semiconductor chip (13) by means of a solder (20) to form a composite lead (22). The second step is carried out if all of the semiconductor chips (12, 13) are proved to have a good quality in an inspection step carried out after the first step.