Abstract: A manufacturing method for a Bi-CMOS by trenching which is allowed to manufacture the bipolar celement and CMOS element simultaneously on one substrate by trench etching, comprising the processes of growing an oxide layer, forming N.sup.+ buried layer, growing n-type epitaxial layer after removing the oxide layer, growing again an oxide layer, a plurality of isolation regions being formed by diffusing a boron impurity, the base regions as well as the collector, emitter and drain regions are formed, the trenched grooves are formed after removing said oxide layer, an oxide layer is grown after inverting the epitaxial layer, the electrode window is opened, and a metal such as alminium is deposited thereby the electrode terminals of base, emitter and collector of bipolar element and also the drain, source and gate of CMOS are drawn out, respectively.

Abstract: A semiconductor fabrication process uses an epitaxial layer as an etch stop in a plasma etch process. In one embodiment, mechanical stops and an epitaxial layer are used in combination for stopping precisely at a desired end point.

Abstract: In a contact type image sensor prepared by disposing a plurality of sandwich type photoelectric conversion elements each of which is obtained by sandwiching an amorphous semiconductor layer as a photoelectric conversion layer between a metal electrode and a light-transmissive electrode, the amorphous semiconductor layer is insulated and separated by means of a silicon oxide layer in every element. The silicon oxide layer is obtained by oxidizing selectively the amorphous semiconductor layer in accordance with the optically assisted anodizing process.

Abstract: A heterojunction bipolar transistor includes a base layer and a wide bandgap emitter layer. A portion of the base layer is exposed, a base electrode is formed thereon and the active region of the emitter-base junction is limited inside a semiconductor body. As a result, surface recombination current generation of the peripheral region of the junction is prevented and the emitter efficiency is improved.

Abstract: The field oxide surrounding an NMOS device or the field oxide around the NMOS device and between the NMOS and PMOS devices in CMOS is split or notched to make at least one thin field oxide region under which a degenerative P+ region is formed in the substrate to increase threshold voltages of the undesired field oxide FET.

Abstract: Herein disclosed is a semiconductor pressure sensor and a method of manufacture. The sensor includes a plate having a recess in its main surface. A diaphragm has a lower surface therof bonded to a first main surface of the plate and formed so as to have an upper surface having no holes therein. A piezoresistive layer is formed so as to be in contact with the diaphragm and is positioned so as to be at least partially over the recess. The resistance of the piezoresistive layer provides an indication of pressure applied to the diaphragm. The manufacturing method includes forming a piezoresistive layer of a single crystal substrate in a diaphragm without any recrystallization.

Abstract: A conducting link is disposed in an insulating layer of a semiconductor device in combination with a plurality of wirings of the device which are electrically separated from each other. The conducting link is selectively activated to provide the wirings with a conducting path, and is activatable by melting metal contained in the wirings by irradiating a portion of the wirings in the vicinity of the link with a shot of a pulse of laser beam. The link comprises a through hole or a trench disposed in the insulating layer depending on the structural configuration of the device. The method of fabricating and activating the conductive link is provided.

Abstract: The method involves the formation above the substrate of regions of epitaxial type automatically aligned with the gate electrode and designed to form the source and drain regions of the transistor. These regions are doped by ion implantation using a comparatively low implantation energy such that the doping agent does not penetrate into the substrate. By providing the source and drain junctions on the surface of the substrate, rather than in the substrate, there are no lateral junction capacitances and the horizontal dimensions of the IGFET may be reduced, with the result that high response speeds and high integration densities are obtained.

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter structure (60). A collector region (90) and an extrinsic base region (100) are formed in the semiconductor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.

Abstract: A technique for providing a radiation formable conductive link in an integrated circuit comprising the steps of: depositing a plurality of aluminum conductors on an exposed surface of an otherwise completed integrated circuit, and forming a bridge of amorphous silicon layer joining the aluminum conductors at selected locations, whereby subsequent laser radiation produces diffusion of aluminum into the amorphous silicon, producing a highly conductive aluminum doped silicon bridge.

Abstract: Heterojunction bipolar transistor technology employing in a body wherein a larger area base electrode over a buried electrode has above it a smaller area electrode, an overhang capability on the portion of the smaller area electrode that operates to mask the base layer in converting the extrinsic portion to high conductivity and assist lift-off of base contact metal such that the base contact metal is in extremely close proximity to the smaller area electrode.

Abstract: A fabrication method for a high speed and high packing density semiconductor device (BiCMOS) in which high speed polysilicon self-aligned bipolar transistors and high packing density CMOS are contained on the same wafer in such a manner that simplicity in fabrication is attained, while the high speed of operation and the high packing density of array are simultaneously realized.

Abstract: The invention comprises an improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the transistors in the memory cell, said buried layer being located sufficiently close to a base layer in only the memory portion of the device to provide a sufficiently high capacitance between said buried layer and said base layer to prevent the occurrence of a soft error caused by an alpha particle striking the structure without interfering with the speed of the device.

Abstract: A composite buffer layer is formed with a layer of GaAs on a semi-insulating GaAs substrate. Next a short period superlattice is formed followed by another GaAs layer, whereon is formed a first AlGaAs layer having a first mole fraction of Al and a second AlGaAs layer having a second mole fraction of Al higher than the first mole fraction. As intrinsic GaAs channel layer is formed on the second AlGaAs layer.

Abstract: A method for preferentially etching phosphosilicate glass to form a micromechanical structure includes forming a layer of phosphosilicate glass on a substrate and opening at least one via in the phosphosilicate glass layer. A layer of material which is patterned to produce a micromechanical structure is formed over the phosphosilicate glass layer which extends through the via and adheres to the substrate. The phosphosilicate glass layer is then removed by immersing the device in an etchant bath containing an aqueous ammoniacal hydrogen peroxide solution. The resulting micromechanical structure has at least one point of attachment to the substrate and is otherwise spaced apart from the substrate by an air gap. A method for attaching an overhanging mass to a miniature cantilever beam using microelectronics fabrication technology is also provided in which the center of gravity is shifted to the endpoint of the free end of the beam.

Abstract: In a semiconductor integrated circuit fabrication method, isolated regions are in a silicon substrate, which is then covered with polysilicon, a passive base region is then formed, the polysilicon is selectively oxidized, the unoxidized polysilicon is then doped at first and second concentrations, a surface insulating layer is then deposited, the dopant is then diffused from the polysilicon to create further passive and active base regions, contact holes are then opened, the polysilicon above the active base is then doped, and this dopant is then diffused to create an emitter region in the active base. By employing a polysilicon layer with reduced initial thickness, this fabrication method enables precise doping with excellent control over the active base concentration, junction depth, polysilicon sheet resistance, and other parameters.

Abstract: A method of forming semi-conductor devices components wherein there are at least two exposed conducting regions having passivating material overlying said regions. The passivating material is subject to etching by a given etchant. At least one, but less than all of the regions are covered with a material, preferably an electrical conducting material, which also preferably covers additional electrical conducting or semi-conducting regions. Thereafter, all the regions are subjected to the given etchant, but only those regions having the passivating material not covered with the etch resistant material are removed. Preferably, at this point, a layer of conducting material is deposited over all the regions.

Abstract: A process is disclosed for forming high-performance high-voltage PNP transistors in a conventional monolithic, planar, PN junction isolated integrated circuit that contains high-performance NPN transistors. The process permits independently optimizing the NPN and PNP transistors.

Abstract: A method of forming a bipolar transistor comprising the steps of forming a base region in a semiconductor structure and disposing an emitter region on a surface of a first portion of the base region, the emitter region having upper and side surfaces. An active base region is formed in the first portion of the base region and an inactive base region is formed in a second portion of the base region adjacent to the first portion and the side surface of the emitter region. A layer of insulating material is formed over a surface of the inactive base region and over the upper and side surfaces of the emitter region. Portions of such layer are selectively removed to expose the upper surface of the emitter region and a portion of the surface of the inactive base region, and to maintain a region of insulating material between the exposed surface portion of the inactive base region and the side surface of the emitter region.