Abstract: A process for manufacturing an insulated gate field effect semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the gate region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the gate. Contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the gate from the contacts.

Abstract: A method of manufacturing a semiconductor device having a submicron pattern. A p-type semiconductor layer is formed on an n-type semiconductor substrate. Insulating films are formed on the p-type semiconductor layer. A first mask layer, such as an aluminum layer having an etching rate different from that of the insulating films, is formed on the insulating films. A second mask layer having an etching rate different from that of the first mask layer, is formed on the first mask layer. The second mask layer is patterned. A coating film having an etching rate different from that of the first insulating film, is formed on the resultant structure. The coating film is etched to be left on a side wall of the patterned second mask layer. The first mask layer is patterned, using the residual coating film and the patterned second mask layer as masks, and a pattern finer than that of the resist is formed in the first mask layer.

Abstract: A heterojunction bipolar transistor and method of manufacturing the same is disclosed in which, a semi-insulation layer and an external base layer sequentially epitaxially grown on a collector layer are selectively mesa-etched through a mask of an insulation film provided with an opening so that the external base layer, the semi-insulation layer and the collector layer are selectively exposed. Subsequently an internal base layer and an emitter layer are selectively epitaxially grown in sequence on the exposed regions of the external base layer, the semi-insulation layer and the collector layer. An emitter electrode is formed in a self-aligned manner through the opening of the insulation film. Thus, transistor performance is improved and element size accuracy is improved.

Abstract: A method of manufacturing a semiconductor device comprising a semiconductor body (1), of which a surface (13) is provided with a metallization (15,16,17,18) with a thick connection electrode (19). The metallization is formed in a first metal layer (49) and the connection electrode is formed in a second metal layer (51). Between these metal layers is provided a third metal layer (50), which serves as an etching stopper during the formation of the connection electrode. During a single deposition step, the three metal layers (49,50,51) are provided, after which first the connection electrode and then the metallization are formed by etching. By providing the three metal layers in a single deposition step, the number of processing steps for manufacturing the semiconductor device is limited and it is moreover achieved that the adhesion between connection electrode (19) and metallization (15,16,17,18) is an optimum.

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time.Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material.

Abstract: A method of producing an end surface light emmision type semiconductor device comprising: a process of producing a lower cladding layer, an active layer, and an upper cladding layer on a semiconductor substrate; a process of forming a stripe groove of a predetermined depth reaching the lower cladding layer at a predetermined position of the wafer to produce an output end surface; a process of depositing photosensitive material in the groove; a process of producing a required number of lenses from the photosensitive material; and a process of dividing the wafer into a plurality of lens-appended end surface light emission type semiconductor devices.

Abstract: Gate sidewall spacers are created by a two-step procedure in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer (32) of insulating material is conformally deposited and then substantially removed except for small spacer portions (34) adjoining the sidewalls of a doped non-monocrystalline semiconductor layer (20A) destined to become the gate electrode (36). The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts.

Abstract: A semiconductor device comprising a first conductor having first and second portions which are electrically disconnected from each other, and a second conductor, formed on an insulating film separating it from the first conductor, which is electrically conductive. A radiated energy beam renders the second conductor non-conductive, while simultaneously electrically connecting the first and second portions, rendering the first conductor conductive, as needed.

Abstract: A laminated film made of a first insulating film and a second insulating film having a selectivity of etching condition to the first insulating film is selectively formed on a first conductivity type semiconductor substrate to use the substrate under the laminated film as a base and emitter active region forming region. The laminated film remains until an anisotropically dry etching step is finished to prevent the base and emitter active region from damaging due to an etching atmosphere at anisotropically dry etching time.

Abstract: In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.

Abstract: The manufacture of a self-aligned gate contact having a very short gate length measuring, for example, 0.3 to 0.1 micron wherein photolithography is carried out together with isotropic deposition to produce a gate contact having an extremely low lead resistance, the method utilizing a masking element which is removed by a lift-off technique.

Abstract: The formation of a self-aligned semiconductor structure in a semiconductor substrate is described by providing a first and a second layer or a wave guide of different chemical composition above said semiconductor substrate, said second layer providing a shape defining opening permitting chemical conversion of said first layer adjacent said substrate to a third chemical composition different from said first and second layers. The third chemical composition is removed with a reagent that reacts only with said third composition and not with said first and second layers for the manufacture of self-aligned semiconductor structures. The third chemical composition is retained in the formation of a wave guide and has an index of refraction different from the first layer.

Abstract: A semiconductor memory device is provided with a memory region including SAMOS type memory transistors and a non-memory or peripheral region including MOS transistors which are interconnected to form logic circuits such as decoders for controlling the operation of each of said memory transistors. Each of the transistors includes a pair of first and second doped polysilicon layers and an interlayer insulating film provided as sandwiched between the pair of first and second doped polysilicon layers. In the memory region, the first and second doped polysilicon layers define floating and control gate electrodes, respectively; whereas, in the non-memory region, the first and second doped polysilicon layers are electrically interconnected by a through-the-layer electrode formed through the interlayer insulating film.

Abstract: Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO.sub.2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of the step on the SiO.sub.2 layer at a portion corresponding to the lower part of the step, (3) sputter-SiO.sub.2 layer is formed by sputtering on the photoresist layer and SiO.sub.2 layer, (4) another photoresist layer is formed on the sputter-SiO.sub.2 layer, (5) the another photoresist layer and sputter-SiO.sub.2 layer are removed, and (6) the SiO.sub.2 layer and photoresist layer are removed. By this method, semiconductor substrate with flatness of within 50 nm in a 6-inch wafer can be obtained.

Abstract: A method is set forth of manufacturing a bipolar transistor with emitter ballast resistors. According to the invention, a base window and a strip-shaped opening are formed beside each other on a collector region. The strip-shaped opening is first covered by a masking layer and then doping of the base is provided. After removal of the masking layer, oxide layers of the same thickness are formed in the base window and in the strip-shaped opening. After formation of emitter fingers, base contact windows are formed within the base zone, and resistance windows are formed within the strip-shaped opening, whereupon simultaneously base contact zones and mutually separated emitter ballast resistors are formed in these windows.

Abstract: The manufacture of n-channel and p-channel transistors in a CMOS process which involves employing gate spacer oxide layers for of reducing the under-diffusion of the implanted source-drain regions under the gate areas. The spacer oxide widths for the n-channel and the p-channel transistor are set differently so that both transistor types can be optimized independently of one another and without an additional expenditure for more masking steps. The method is employed for the manufacture of large scale integrated circuits for fast switching speeds.

Abstract: A method of fabricating a self-aligned hole-within-a-hole structure which resolves the smaller hole at small dimensions by using a single photolithography step to define the two holes, the step being performed on a planar surface. The method comprises fabricating a block on a substrate having the dimension of the smaller hole, fabricating a sidewall spacer on the block such that the spacer and the block have the dimension of the larger hole, growing a first layer surrounding the sidewall spacer, removing the sidewall spacer, growing a second layer surrounding the block which is thinner than the first layer, and removing the block.

Abstract: Self-adjusted bipolar transistors having reduced extrinsic base resistance are produced by forming an emitterterminal from a polysilicon layer structure and etching free the polysilicon layer structure using the emitter layer structure as a mask. Sidewall insulating layers are provided with a metallically conductive layer. This layer is self-adjusting in relation to the emitter zone and surrounds the emitter in an annular formation. The structure improves the foursided base wiring around the emitter and is used in the production of highly integrated bipolar circuits.

Abstract: A process for manufacturing a bipolar semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the emitter region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the emitter. Conductive contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the base from the contacts.

Abstract: A process for the simultaneous production of bipolar transistors and CMOS transistors on a substrate using very large circuit integration (VLSI) semiconductor technology, modified by additional process steps in such a way that a decoupling of the two types of transistors is obtained with respect to the process. This is achieved by the use of a protective oxide above the active zones of the CMOS transistors during the production of the bipolar-specific base zones and by employing a gate electrode material in two layers, the second layer being used for the emitter and collector zone, resulting in a decoupling of phosphorus doping used for forming MOS gates, and arsenic doping used for polysilicon emitters. The use of the same resist mask for the gate structuring and the production of the emitter contact, and also for the production of the source/drain terminal zones, serves to keep the implanted phosphorus out of the emitter zone.