Abstract: A superlattice film is formed by introducing a mixture of a first gas reactant capable of only plasma-excited chemical reaction and a second gas reactant capable of both plasma-excited chemical reactions into a reaction chamber, discontinuously carrying out plasma-excited chemical reaction, and continuously carrying out light-excited chemical reaction, thereby alternately depositing on a substrate a thin film layer which is formed when the plasma- and light-excited chemical reactions are carried out and another thin film layer which is formed when the plasma-excited chemical reaction is interrupted, thereby forming a thin film of alternately deposited layers.

Abstract: A process for fabricating both bipolar and complementary field effect transistors in an integrated circuit is disclosed. The process begins with a structure having a P type substrate 10, an N type epitaxial layer 15, and an intervening N type buried layer 12. The process includes the steps of removing all of the epitaxial layer 15 and all of the buried layer 12 from regions of the substrate where NMOS devices are to be formed, to thereby leave second regions of the epitaxial layer 15 and buried layer 12 having sidewalls 21 protruding above the substrate 10. A layer of silicon dioxide 25 is formed at least over the sidewalls of the protruding regions, and then a further epitaxial deposition of silicon is employed to reform the epitaxial layer 28 over the first regions, which epitaxial layer 28 is separated from the previously formed epitaxial layer 15 by the silicon dioxide isolation 25. The process continues by fabricating bipolar and field effect transistors in separate ones of the first and second regions.

Abstract: A self-aligned process for the fabrication of a walled-emitter transistor includes the formation of an isolated device island on the surface of a semiconductor wafer. A layer of dielectric is then formed on the wafer, leaving only part of the device island exposed. A `substitute emitter` of silicon nitride is then formed on the exposed part of the device island in the position which will subsequently be occupied by the emitter. The exposed surface of the device island is then oxidized, some oxide being formed beneath the periphery of the substitute emitter. Oxide spacers are then formed non-lithographically about the periphery of the substitute emitter, after which the substitute emitter is removed and a base is formed in the semiconductor thus exposed. An emitter is then formed in the exposed semiconductor.

Abstract: A method of manufacturing semiconductor devices is set forth using reactive ion plasma etching in which an optical grating is formed to etch underlying regions, such as dielectric material, semiconductor material, or alternate layers of different semiconductor material. The optical grating is formed with a rectangular profile having grooves and mask strips on a sample material where each of the grooves has a width L.sub.S substantially equal to the width L.sub.M of the mask strips. The optical grating is formed of a material which may be one of a photoresist, a dielectric compound, a metal, or a metallic compound. This method enables control of reactive ion etching during manufacture of integrated circuits of III-V compounds.

Abstract: A method of producing an integrated circuit device having a bipolar transistor and P-channel and N-channel MOS transistors (Bi-CMOS IC) is disclosed. This method includes the steps of forming a collector contact hole, depositing a polycrystalline silicon layer after formation of the collector contact hole, and diffusing impurities through the polycrystalline silicon layer into a collector region through the collector contact hole to form a collector contact region. The polycrystalline silicon layer doped with impurities is employed as a collector electrode and gate electrodes. The impurities in the collector contact region are re-diffused into the collector region by the subsequent heat treatments used in forming an emitter region and source and drain regions of the respective MOS transistors. A Bi-CMOS IC in which the collector resistance of the bipolar transistor is lowered is thereby produced without a great increase in manufacturing steps.

Abstract: A semiconductor substrate including a top epitaxial compound layer comprising: a single-crystalline semiconductor wafer substrate; a strained layer superlattice (SLS) structure layer having a lattice constant varying from that of the wafer substrate to that of the top compound semiconductor layer and formed on the wafer substrate; a semiconductor buffer layer having the same lattice constant as that of the top compound semiconductor layer and formed on the SLS structure layer; another SLS structure layer for filtering dislocations having a fixed lattice constant equal to that of the top semiconductor layer and formed on the buffer layer; and the top semiconductor layer formed on the another SLS structure layer.

Abstract: A method of simultaneously forming recesses for via holes and tube structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single aperture such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ground plane conductor.

Abstract: An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

Abstract: A method for manufacturing a semiconductor device with a lens section. A semiconductor element is formed in a semiconductor substrate and a transparent layer is formed on this semiconductor element. The transparent layer is patterned to form the lens section.

Abstract: A method for preferentially etching phosphosilicate glass to form a micromechanical structure includes forming a layer of phosphosilicate glass on a substrate and opening at least one via in the phosphosilicate glass layer. A layer of material which is patterned to produce a micromechanical structure is formed over the phosphosilicate glass layer which extends through the via and adheres to the substrate. The phosphosilicate glass layer is then removed by immersing the device in an etchant bath containing an aqueous ammoniacal hydrogen peroxide solution. The resulting micromechanical structure has at least one point of attachment to the substrate and is otherwise spaced apart from the substrate by an air gap. A method for attaching an overhanging mass to a miniature cantilever beam using microelectronics fabrication technology is also provided in which the center of gravity is shifted to the endpoint of the free end of the beam.

Abstract: A process is used to form in a common substrate a PMOS transistor of the lightly doped drain (LDD) type, an NMOS transistor of the LDD type and a vertical n-p-n bipolar transistor. In particular: the steps used to form an n-type well for the PMOS transistor, and an n-type drain extension well for the NMOS transistor, are also used to form the n-type collector of the bipolar transistor; the steps used to form the p-type extension well for the PMOS transistor are also used to form the p-type base of the bipolar transistor, the source/drain implantation step for the NMOS transistor is also used to form the emitter and a contact region for the collector of the bipolar transistor; and the source/drain implantation step for the PMOS transistor is used to form a contact region for the base of the bipolar transistor.

Abstract: An improved textured surface of a photovoltaic device is provided by an anisotropic etching process in which pyramidal structures are formed on a silicon surface having a (100) crystallographic orientation. An aqueous solution of an alkali metal hydroxide is heated to approximately 85.degree. C. whereupon isopropyl alcohol is added. Separated silicon wafers are immersed in the solution for approximately 45 minutes. The wafers can be agitated for a limited time in the solution, and preferably the wafers and solution are covered during the etching step. The resulting pyramids are on the order of 14 microns high and 20 microns on each side of the base. The overlap of the pyramids provides desired random locations for the pyramids.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.A novel process of forming vertical (e.g.

Abstract: A bipolar transistor structure (1) which can be used in an integrated circuit where bipolar (1) and CMOS transistors (2,3) are formed simultaneously on one substrate. In integrated circuit form the material, for example polycrystalline silicon, used for the gates (11,21) of the CMOS transistors is also used for the emitters (29) of the bipolar transistors, the collectors of the bipolar devices are comprised by doped wells (5) in the substrate (4) and the base contacts of the bipolar devices are comprised by regions (27,27a) equivalent to source and drain regions (17,18) of the n-well MOS transistors and bridged by base implants (28). The conventional CMOS processing is modified by the addition of two masking steps and one implant (base implant).

Abstract: A method for forming an array of antifuse structures on a semiconductor substrate which previously has had CMOS devices fabricated thereupon up to first metallization. A fuse structure is formed as a sandwich by successively depositing a bottom layer of TiW, a layer of amorphous silicon, and a top layer of TiW. The amorphous silicon is formed in an antifuse via formed in a dielectric layer covering the bottom layer of TiW. First metallization is deposited and patterned over the top layer of TiW. An intermetal dielectric layer is formed over the fuse array and second metal conductors are formed thereupon. An alternative embodiment includes forming an oxide sidewall spacer around the periphery of an antifuse structure. Connection resistance to the bottom layer of TiW is lowered by using a number of vias between the second-metal conductors and the bottom layer of TiW in a row of an array of antifuse devices.

Abstract: A semiconductor device is programmed by a laser beam which causes an insulator between two conductors on a silicon substrate to be permanently altered, as by breakdown of the insulator. The conductors may be metals such as aluminum or tungsten, and the insulator is a layer of deposited or thermal silicon oxide. The breakdown may be enhanced by voltage applied between the conductors while the laser beam is focused on the structure.

Abstract: In the invention, the width of the emitter contact layer is determined in accordance with the width of a first side wall, and the junction distance between a base contact layer and the emitter contact layer is determined in accordance with the width of a second side wall. The junction distance between the emitter contact layer and the base contact layer can be decreased, no extra high-temperature annealing such as thermal oxidation is needed, and the diffusion profile can be controlled to be shallow.

Abstract: A semiconductor device includes a plurality of crystalline layers successively disposed directly on a substrate or on a buffer layer on the substrate and a getter layer comprising a metal of high activity disposed between the substrate or the buffer layer and the plurality of crystalline layers. An MO-CVD crystal growth method for growing a plurality of crystalline layers successively on a substrate or on a substrate having a buffer layer by supplying gases to a reaction tube containing a substrate includes growing a getter layer, including a metal of high activity for removing impurities, on the substrate or the buffer layer before growing a target crystalline layer.

Abstract: A method for the manufacture of a planar, self-aligned emitter-base complex, whereby a semiconductor layer structure standard for hetero-bipolar transistors is first grown on a substrate, the base regions are subsequently etching through a mask technique and are provided with the base metallization and with a first dielectric layer and insulation implantations and spacers for electrical insulation of the base are manufactured, and, following thereupon, the emitter region is provided with the emitter metallization and with a third dielectric layer.

Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surrounding the buried layer. The buried layer serves as a collector and it is surrounded by an isolation area. The top two epitaxial layers are of a conductivity type opposite to that of the substrate with the upper most epitaxial layer having a higher dopant density than does the middle epitaxial layer. A master mask is used to provide self-alignment between the isolation area, a collector plug which makes contact to the buried layer, and a base region.