Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

Abstract: Disclosed is a method of producing a bipolar transistor which enables an external base region, an intrinsic base region and an emitter region to be formed in self-alignment with respect to the base electrode. More specifically, the method comprises the steps of side-etching an insulating film formed underneath the base electrode by a wet etching process to provide an undercut portion, depositing polycrystalline silicon so as to extend into the undercut portion by low pressure CVD to thereby fill the undercut portion with the polycrystalline silicon, and subjecting the polycrystalline silicon to thermal oxidation, thereby simultaneously forming a sidewall spacer whereby the base electrode and the emitter electrode are electrically isolated from each other and an oxide film on the emitter forming region, the oxide film having high selectivity in anisotropic etching with respect to the substrate (silicon).

Abstract: The invention provides a method for manufacturing integrated circuits.For forming circuits incorporating bipolar transistors by CMOS technology r a low cost price, a succession of steps are carried out using only 9 successive masks so as to obtain more particularly a lateral NPN bipolar transistor in a P caisson on an N substrate. The source and drain contacts are made from metal silicide, as well as the base contact. The emitter and collector contacts are made from polycrystalline silicon covered with silicide. The N transistor is self aligned with a low access resistance and a low junction depth. The ionic source and drain implantation of the TMOSP on the one hand and of the bipolar base on the other is common. In addition, the access resistance to the P type transistor and gate covering over the sources and drains of this transistor are minimized while leaving a great latitude of choice for doping of the base of the bipolar transistor.

Abstract: A bipolar transistor structure wherein the emitter zone is produced by outward diffusion from etching residues which are formed by deposition of conductive material and re-etching, with the etching residues forming part of the emitter terminal region. In addition to individual transistors, pairs of transistors having coupled emitters can also be produced and employed in hig precision differential amplifiers. Memory cells can also be produced which have low surface requirements, particularly due to the reproduceable attainment of emitter widths below one micron. Since the methods enable the production of completely self-aligned transistors, they can be implemented with straightforward steps which are largely independent of lithography. Emitter widths in the range of about 0.2 to 0.5 microns can be produced.

Abstract: A semiconductor device comprising a semiconductor substrate with at least one semiconductor region formed in it, a polycrystalline silicon layer formed in contact with the semiconductor region and a metal layer formed on the polycrystalline silicon layer. The peripheral portion and outer edges of the polycrystalline silicon layer are covered with an insulation layer.

Abstract: A process for chemically modifying spin-on-glass (SOG) for improved performance in semiconductor device fabrication is disclosed. To compensate for severe surface topographies associated with very large scale integration (VLSI) technology, a thicker non-etch back SOG process is utilized for forming a SOG layer over a chemical vapor deposition (CVD) layer. A single layer of SOG is formed over the CVD layer, providing planarizing coverage over formational or growth defects. The silylation of the SOG layer provides for the formation thicker single layers of SOG and significantly reduces the wet etching rate in diluted HF.

Abstract: According to the invention, on a silicon substrate is formed an insulation silicon oxide film with the etching rate thereof increasing as one goes away from the substrate, on the insulation silicon oxide film is formed a first silicon nitride film defining the width of the element isolation region, the insulation silicon oxide film is provided with a slope by isotropic etching with the first silicon nitride film as mask, and a lower portion of the insulation silicon oxide film is isotropically etched, with the sloped portion of the insulation silicon oxide film being masked by a second silicon nitride film.

Abstract: A self aligned method of fabricating a self aligned semiconductor device employs an initial step in which a first window having an inner perimeter and outer perimeter is opened through a first protective layer situated atop a semiconductor substrate, to divide the substrate into three separate zones. The window exposes a first surface portion of the semiconductor substrate and circumferentially defines or encompasses a second central portion of the protective layer as well as a second unexposed surface portion of the substrate. A third surface portion of the substrate lies beyond the outer perimeter of the first window. Precisely aligned substrate regions of the same or different conductivity type can be established by using differentially etchable materials to mask designated surface portions of the substrate.

Abstract: Integrated semiconductor circuits with at least one bipolar transistor (17) and at least one MOS field effect transistor (18) on a chip wherein contacts from a metal interconnect level to diffused active emitter (8) and collector (5) regions of the bipolar transistor (17) as well as the gate electrode (9) of the MOS transistor are composed of a high melting point silicide, such as tantalum, tungsten, molybenum or titanium silicide, are disclosed, along with a method of producing such circuits. In addtion to achieving independence from a metallization grid and achieving low-resistance wiring, the use of the silicide, in conjunction with the high temperature stability of silicides, enables its simultaneous use as an implantation mask. The invention allows the production of bipolar/MOS components on a chip without added outlay.

Abstract: A well structure for a semiconductor device has a dopant profile such that the maximum net dopant level is below the device surface. This is achieved by a two stage doping with materials of opposite conductivity type.

Abstract: A method of fabricating a bipolar transistor on a semiconductor substrate capable of operating at a high operating speed and formed in a compact construction. A first polycrystalline silicon layer is oxidized selectively to form areas for forming base electrodes and a collector electrode. Boron is implanted into the polycrystalline silicon layer in a high concentration to form the base electrodes, the silicon dioxide film is removed to form an opening from a region for forming an emitter, the side wall of the opening is oxidized, an inactive base is formed in the polycrystalline silicon layer, active base is formed in the inactive base by implanting boron in the inactive base. Then, the entire surface of the device is coated with an oxide film and a second polycrystalline silicon layer.

Abstract: A metal layer is formed by selective CVD method on an emitter region formed by using a field oxide film as a mask. Opening for ion-implanting an impurity for forming external base region is formed in the field oxide film by utilizing the metal layer and a metal layer creep up a bird's beak of the field oxide film as masks. An impurity is doped in a semiconductor substrate through the opening formed in the field oxide film to form external base region. The distance between the emitter region and external base region is controlled by a length of the metal layer creep up the bird's beak.

Abstract: A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a long, narrow collector region. An N-type collector is implanted in the collector region. The implants are diffused to form a shallow gradient P-N junction. Then, device features requiring a predetermined spacing and size are photolithographically defined along the length of the collector region. The device features and the collector region are made long enough for the features to readily transect the collector region even if the mask is misaligned. The active transistor and the collector, base and emitter contacts are self-aligned with the collector region so as to take advantage of the noncritical spacing of the preceding steps. A single polysilicon layer used to form base, collector and emitter contacts and a triple diffusion transistor.

Abstract: An improved method for fabricating a bipolar transistor reduces base current resistance which heretofore has limited the switching frequency and current handling ability of bipolar transistors. The transistor base and emitter are formed as a diffusion through an emitter contact pedestal formed on an epitaxial layer over a substrate. Access to the n-type emitter is through the emitter contact pedestal while access to the lightly doped p-type base is through a nearby heavily doped p-type base insert. Electrical isolation between the pedestal and the base insert is ensured by forming oxide sidewall spacers on the emitter contact pedestal during the implant used to form the base insert. Defining the isolation with sidewall spacers permits reliable isolation of emitter and base insert while minimizing their physical separation.

Abstract: A transistor is formed according to the solid phase epitaxial growth which is one of the semiconductor integrated circuit device manufacturing techniques. A low-concentration impurity region is formed by selective solid phase epitaxial growth instead of using an epitaxial substrate. The solid phase epitaxial growth is performed twice, when a collector region is formed and when a base region is formed. The depth of collector and base regions are determined by the thickness of the solid phase growth layers, respectively.

Abstract: A method and product for monocrystalline semiconductor buried layer contacts formed from recrystallized polycrystalline buried layers.

Abstract: A method of manufacturing a bipolar transistor (1) with semi-self-aligned p.sup.+ base contacts (27,27a). A p-type base region (28) is formed in a surface region of an n-type region 5 comprising a collector. An element (29) of, for example, n.sup.+ doped polycrystalline silicon, and comprising an emitter, is formed on the surface in contact with the base region (28). The base contacts (27,27a) are formed by implantation and using the element (29) as a mask. An n.sup.+ collector contact (25) is made to the n-tpe region (5).

Abstract: A bipolar transistor with a laterally elongated emitter and base so a laser can diffuse dopant from that emitter through that base to the corresponding collector.

Abstract: An improved process for fabricating modified isoplanar integrated circuits with enhanced density incorporates a number of interactive and co-acting process steps. First, oxide isolation of epitaxial islands is effected in a two step process, forming a thin thermally grown oxide layer (32), over the surfaces of shallow trenches and then filling the shallow trenches with deposited low temperature oxide (34). Second, an enhanced single polycrystalline or polysilicon layer process uses a blanket implant, eliminates certain masking and etching steps, and defines the polycrystalline layer. Third, a new method and structure is provided for dielectrically isolating and separating contact locations on different surface levels of the integrated circuit structure adjacent to step locations between the surface levels. Finally, a new method constitutes all of the electrical contact locations for the elements of the integrated circuit structure at the same substantially isoplanar level.

Abstract: An improved method for the etch-back planarization of interlevel dielectric layers provides for cessation of the etch-back upon exposure of an indicator layer. the indicator layer, usually a metal, metal nitride, or silicon nitride is formed either within the dielectric or over an underlying metallization layer prior to patterning by conventional photolithographic techniques. A sacrificial layer, typically an organic photoresist, is then formed over the dielectric layer. Because of the presence of both relatively narrow and relatively broad features in the metallization, the thickness of the sacrificial layer will vary over features having different widths. As etch back planarization proceeds, the indicator layer which is first encountered releases detectable species into the planarization reactor. Detection of these species indicates that removal of the overlying dielectric layers to a predetermined depth is achieved.