Patents Examined by Kiesha R Bryant
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MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification
Patent number: 7960233Abstract: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.Type: GrantFiled: August 21, 2010Date of Patent: June 14, 2011Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sik K. Lui, Anup Bhalla -
Patent number: 7956387Abstract: A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.Type: GrantFiled: September 8, 2006Date of Patent: June 7, 2011Assignee: Qimonda AGInventor: Till Schloesser
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Patent number: 7956465Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.Type: GrantFiled: January 20, 2010Date of Patent: June 7, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Cheng-Lin Huang
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Patent number: 7952157Abstract: An electromagnetic shielding device in an infrared receiver comprises of a wiring frame (4) of metal and an electromagnetic shielding cover (1) of metal. There is a window (2) in the electromagnetic shielding cover (1), in which there is provided a shielding net (3). The electromagnetic shielding cover (1) has a protruding tongue (6) in the bottom of its both sides respectively and the protruding tongues (6) are bent downwards and entad to engage on the wiring frame (4), thus forming an electromagnetic shielding structure transparent to a chip inside. The electromagnetic shielding device of the present invention is simple in structure, reasonable in design, easy to manufacture, low-cost, high qualified ratio and thus suitable for mass productivity. The electromagnetic shielding device improves the electromagnetic interference preventive capability of a semiconductor element and thus increases the sensibility and reliability of an infrared receiver.Type: GrantFiled: November 20, 2006Date of Patent: May 31, 2011Inventor: Jiaxiang Yang
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Patent number: 7952109Abstract: An apparatus comprising a structure comprising a group III-nitride and a junction between n-type and p-type group III-nitride therein, the structure having a pyramidal shape or a wedge shape.Type: GrantFiled: July 10, 2006Date of Patent: May 31, 2011Assignee: Alcatel-Lucent USA Inc.Inventor: Hock Min Ng
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Patent number: 7952105Abstract: A light-emissive device includes a substrate having a first electrode formed on the substrate. A colloidal light-emitting layer comprising inorganic, light-emissive particles is formed over the first electrode. A second electrode is formed over the light-emitting layer. At least one of the first and second electrodes is transparent. The transparent electrode preferably has a refractive index substantially equal to or greater than the refractive index of the colloidal light-emitting layer. Finally, a light-scattering layer is formed on a side of the transparent electrode opposite the colloidal light-emitting layer.Type: GrantFiled: January 29, 2007Date of Patent: May 31, 2011Assignee: Global OLED Technology, LLC.Inventor: Ronald S. Cok
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Patent number: 7951642Abstract: Materials, devices, and methods for enhancing performance of electronic devices such as solar cells, fuels cells, LEDs, thermoelectric conversion devices, and other electronic devices are disclosed and described. A diamond-like carbon electronic device can include a conductive diamond-like carbon cathode having specified carbon, hydrogen and sp2 bonded carbon contents. In some cases, the sp2 bonded carbon content may be sufficient to provide the conductive diamond-like carbon material with a visible light transmissivity of greater than about 0.70. A charge carrier separation layer can be coupled adjacent and between the diamond-like carbon cathode and an anode. The conductive diamond-like carbon material of the present invention can be useful for any other application which can benefit from the use of conductive and transparent electrodes which are also chemically inert, radiation damage resistance, and are simple to manufacture.Type: GrantFiled: June 29, 2010Date of Patent: May 31, 2011Inventor: Chien-Min Sung
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Patent number: 7948055Abstract: An inductor formed on a semiconductor substrate is provided in the present invention. The inductor comprises a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.Type: GrantFiled: August 31, 2006Date of Patent: May 24, 2011Assignee: United Microelectronics Corp.Inventors: Tsun-Lai Hsu, Jun-Hong Ou, Jui-Fang Chen, Ji-Wei Hsu
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Patent number: 7947540Abstract: A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.Type: GrantFiled: February 8, 2007Date of Patent: May 24, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Han-Sin Lee
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Patent number: 7939351Abstract: The present invention provides a production method for a nitride semiconductor light emitting device, which warps less after removing the substrate, and which can emit light from the side thereof; specifically, the present invention provides a production method for a nitride semiconductor light emitting device comprising: forming stacked layers by stacking at least an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate in this order; forming grooves which divide the stacked layers so as to correspond to nitride semiconductor light emitting devices to be produced; filling the grooves with a sacrifice layer; and forming a plate layer on the p-type semiconductor layer and the sacrifice layer by plating.Type: GrantFiled: September 14, 2006Date of Patent: May 10, 2011Assignee: Showa Denko K.K.Inventors: Hiroshi Osawa, Takashi Hodota
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Patent number: 7939825Abstract: A solid-state image pickup device 1 includes a semiconductor substrate 10, light receiving unit 14 and light shielding film 20. The solid-state image pickup device 1 is back surface incident type and photoelectrically converts light indent on the back surface S2 of the semiconductor substrate 10 from an object into electrical charges and receives electrical charges produced by photoelectric conversion at the light receiving unit 14 to image the object. The light receiving unit 14 forms a PN junction diode with the semiconductor substrate 10. The light shielding film 20 is provided over a front surface S1 of the semiconductor substrate 10 so as to cover the light receiving unit 14. The light shielding film 20 serves to shield light incident on the front surface S1 from the outside of the solid-state image pickup device 1.Type: GrantFiled: July 6, 2007Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventor: Yasutaka Nakashiba
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Patent number: 7939408Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.Type: GrantFiled: December 16, 2010Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-yong Choi, Dong-gun Park, Yun-gi Kim, Choong-ho Lee, Young-mi Lee, Hye-jin Cho
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Patent number: 7939941Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.Type: GrantFiled: June 27, 2007Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Chiou, Chen-Hua Yu, Weng-Jin Wu
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Patent number: 7935556Abstract: A micro electromechanical system and a fabrication method thereof, which has trenches formed on a substrate to prevent circuits from interfering each other, and to prevent over-etching of the substrate when releasing a microstructure.Type: GrantFiled: August 27, 2007Date of Patent: May 3, 2011Assignee: Memsmart Semiconductor Corp.Inventors: Li-Ken Yeh, I-Hsiang Chiu
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Patent number: 7935545Abstract: The present invention includes a method of performing a double-patterning (DP) processing sequence using a plurality of Site-Dependent (S-D) procedures, the method including receiving a first set of wafers by one or more subsystems in a processing system, creating one or more first patterned layers on a first set of patterned wafers, establishing first confidence data for the first set of patterned wafers, establishing a first set of high confidence wafers, creating one or more second patterned layers on a second set of patterned wafers, establishing second confidence data for the second set of patterned wafers and establishing a second set of high confidence wafers.Type: GrantFiled: March 30, 2007Date of Patent: May 3, 2011Assignee: Tokyo Electron LimitedInventors: Mark Winkler, Thomas Winter
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Patent number: 7936001Abstract: In a pair of adjacent stack contact and stack contact in the semiconductor device, the plugs and the plugs are disposed so that a center-to-center distance of the plugs extending through a second interlayer insulating film, which is thicker than the first interlayer insulating film, is larger than a center-to-center distance of the plugs extending through the first interlayer insulating film.Type: GrantFiled: September 6, 2007Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventor: Akio Ohno
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Patent number: 7932552Abstract: Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.Type: GrantFiled: August 3, 2007Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Anthony R. Bonaccio, Joseph A. Iadanza
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Patent number: 7932511Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.Type: GrantFiled: March 1, 2007Date of Patent: April 26, 2011Assignee: Nanosys, Inc.Inventors: Xiangfeng Duan, Chunming Niu, Stephen Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence Bock, David Stumbo, J. Wallace Parce, Jay L. Goldman
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Patent number: 7927991Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes that use a photoresist and simplifying the process is provided, which improves throughput. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or a semiconductor layer is manufactured without using a lithography technique that uses a photoresist. The etching mask is formed of a light absorption layer including a material which absorbs a laser beam. The mask is formed by irradiating the light absorption layer with a laser beam through a photomask and utilizing laser ablation by energy of the laser beam absorbed by the light absorption layer.Type: GrantFiled: August 15, 2007Date of Patent: April 19, 2011Assignee: Semiconductor Energy laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Yasuhiro Jinbo, Eiji Higa, Shunpei Yamazaki
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Patent number: 7928507Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.Type: GrantFiled: December 9, 2009Date of Patent: April 19, 2011Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yu Wang, Tiesheng Li, Sung-Shan Tai, Hong Chang