Abstract: A semiconductor module includes a first metal foil; an insulating sheet mounted on a top surface of the first metal foil; at least one second metal foil mounted on a top surface of the insulating sheet; at least one semiconductor device mounted on the second metal foil; and a resin case for surrounding the first metal foil, insulating sheet, second metal foil, and semiconductor device. A bottom end of a peripheral wall of the resin case is located above a bottom surface of the first metal foil. A resin is provided inside the resin case to fill the inside of the resin case. The bottom surface of the first metal foil and the resin form a flat bottom surface so that the flat bottom surface contacts an external mounting member.

Abstract: A magnetic memory includes a magnetic tunneling junction element having a reference layer, a tunnel barrier layer and a recording layer laminated in order, with information being written to the recording layer in accordance with spin injection magnetization reversal caused by a current, and information written to the recording layer being read out using a current. The magnetic tunneling junction element is disposed on a plug connected to a selection transistor, and a sidewall insulating film covering a side portion of the recording layer of the magnetic tunneling junction element is formed.

Abstract: A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region.

Abstract: To reduce the voltage required to cause a phase transition from an amorphous phase to a crystalline phase, a phase-change memory device (1) comprises: a first electrode (6); a second electrode (8); and a memory layer (14) provided between the first (6) and second (8) electrodes, wherein the memory layer (14) includes at least a first layer (10) formed from a phase-change material which is stable in either the amorphous phase or the crystalline phase at room temperature, and a second layer (12) formed from a resistive material, and wherein the resistance value of the second layer (12) is smaller than the resistance value of the first layer (10) in the amorphous phase, but is larger than the resistance value of the first layer (10) in the crystalline phase.

Abstract: A cell based integrated circuit chip includes a top voltage supply rail and a bottom voltage supply rail and a plurality of metal layers defining at least one filler cell. The filler cell is formed by a first field effect transistor of a first type conductivity, typically an n-channel MOSFET. The source or drain electrodes of the n-channel MOSFET are arranged to as act as a capacitor with respect to the bottom voltage supply rail and to which at least one of the source and drain electrodes is connected. A second field effect transistor of an opposite-type conductivity to the first field effect transistor, typically a p-channel MOSFET, is also provided. The source or drain electrodes of the p-channel MOSFET are connected in series between the top voltage supply rail and a gate electrode of the n-channel MOSFET. The gate electrode of the p-channel MOSFET is connected to a source of ground potential via a resistor.

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.

Abstract: A method of manufacturing a vertical GaN-based LED comprises forming a light emission structure in which an n-type GaN-based semiconductor layer, an active layer, and a p-type GaN-based semiconductor layer are sequentially laminated on a substrate; etching the light emission structure such that the light emission structure is divided into units of LED; forming a p-electrode on each of the divided light emission structures; filling a non-conductive material between the divided light emission structures; forming a metal seed layer on the resulting structure; forming a first plated layer on the metal seed layer excluding a region between the light emission structures; forming a second plated layer on the metal seed layer between the first plated layers; separating the substrate from the light emission structures; removing the non-conductive material between the light emission structures exposed by separating the substrate; forming an n-electrode on the n-type GaN-based semiconductor layer; and removing portions

Abstract: The micro-sensor for a micro image pick-up device includes a flexible circuit board and a circuit substrate. The flexible circuit board has an opening exposing an end of a plurality of metal wires. An image sensing device that electrically connected to a plurality of printed wires disposed on the circuit substrate. The circuit substrate is disposed at the opening of the flexible circuit board. The plurality of printed wires on the circuit substrate corresponds to and contacts the end of the plurality of metal wires exposed out of the flexible circuit board. With the design of the flexible circuit board, the steps of forming a plurality of wiring ducts on the circuit substrate and electrically connecting the printed wires of the circuit substrate by a plurality of connecting lines for transferring signals can be omitted.

Abstract: A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

Abstract: A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat.

Abstract: An organic thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a data line disposed on the substrate; an insulating layer disposed on the data line and having a contact hole exposing the data line; a first electrode disposed on the insulating layer and connected to the data line through the contact hole; a second electrode disposed on the insulating layer; an organic semiconductor disposed on the first and the second electrodes; a gate insulator disposed on the organic semiconductor; and a gate electrode disposed on the gate insulator.

Abstract: A method for manufacturing an optical device comprises steps of: (a) laminating a first, a second, a third, a fourth, a fifth, and a sixth semiconductor layers; (b) patterning at least the third, fourth, fifth and sixth semiconductor layers, thereby forming a light emitting device section and a rectification section; (c) forming first and second electrodes for driving the light emitting device section; and (d) connecting the fourth and sixth semiconductor sections between the first and second electrodes in parallel with the light emitting device section so as to have a rectification action in a reverse direction with respect to the light emitting device section, wherein the step (b) includes conducting etching until a portion of a top surface of the third semiconductor layer is exposed.

Abstract: A dual band photodetector for detecting infrared and ultraviolet optical signals is disclosed. Aspects include homojunction and heterojunction detectors comprised of one or more of GaN, AlGaN, and InGaN. In one aspect ultraviolet/infrared dual-band detector is disclosed that is configured to simultaneously detect UV and IR.

Abstract: A reflectance-controlling layer whose reflectance to irradiation of laser light becomes lower as a thickness thereof becomes thinner is formed on a semiconductor substrate having a first region and a second region. Thereafter, the reflectance-controlling layer on the first region is etched. Then, a laser light is irradiated to the semiconductor substrate to anneal an n?-type semiconductor region and an n+-type semiconductor region of the first region. In the same manner, after the reflectance-controlling layer is formed on the semiconductor substrate, the reflectance-controlling layer on the second region is etched. Then, a laser light is irradiated to the semiconductor substrate to anneal a p?-type semiconductor region and a p+-type semiconductor region of the second region.

Abstract: In accordance with an aspect of the invention, a stacked microelectronic package is provided which may include a plurality of subassemblies, e.g., a first subassembly and a second subassembly underlying the first subassembly. A front face of the second subassembly may confront the rear face of the first subassembly. Each of the first and second subassemblies may include a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge. The second subassembly may have a plurality of rear contacts exposed at the rear face. The second subassembly may also have a plurality of rear traces extending from the rear contacts about the at least one edge. The rear traces may extend to at least some of the plurality of front contacts of at least one of the first or second subassemblies.

Abstract: A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other.

Abstract: Provided is a novel method for manufacturing a field effect transistor. Prior to forming an amorphous oxide layer on a substrate, ultraviolet rays are irradiated onto the substrate surface in an ozone atmosphere, plasma is irradiated onto the substrate surface, or the substrate surface is cleaned by a chemical solution containing hydrogen peroxide.

Abstract: A GaN crystal substrate has a crystal growth surface on which a crystal is grown, and a rear surface opposite to the crystal growth surface. The crystal growth surface has a roughness Ra(C)of at most 10 nm, and the rear surface has a roughness Ra(R) of at least 0.5 ?m and at most 10 ?m. A ratio Ra(R)/Ra(C) of the surface roughness Ra(R) to the surface roughness Ra(C) is at least 50. Thus, a GaN crystal substrate of which front and rear surfaces are distinguishable from each other is provided, without impairing the morphology of a semiconductor layer grown on the GaN crystal substrate.

Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.