Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: An improved light emitting heterostructure and/or device is provided, which includes a contact layer having a contact shape comprising one of: a clover shape with at least a third order axis of symmetry or an H-shape. The use of these shapes can provide one or more improved operating characteristics for the light emitting devices. The contact shapes can be used, for example, with contact layers on nitride-based devices that emit light having a wavelength in at least one of: the blue spectrum or the deep ultraviolet (UV) spectrum.

Abstract: A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes.

Abstract: A semiconductor device that attenuates light to the circuit element area is provided. The semiconductor device includes light-sensitive element area formed on substrate and a circuit element area formed on the substrate. Additionally, a multilayer wiring area is formed on circuit element area. A Tantalum film (which is generally made of tantalum or a tantalum compound) is formed on the surface of the multilayer wiring area to attenuate incident light on circuit element area.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain tungsten and monolayers that contain indium are deposited onto a substrate and subsequently processed to form tungsten-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Abstract: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix.

Abstract: After forming a gate electrode (4a) in a first step, a gate insulating film (5), a semiconductor film (8) and a conducting film (12) including a transparent conducting film (9) are stacked, and on the thus obtained multilayered body (18), a resist pattern (13a) including a first opening (14a) for exposing the conducting film (12) therein and a second opening (14b) having a bottom portion (B) above the gate electrode (4a) is formed. Portions of the conducting film (12) and the semiconductor film (8) exposed in the first opening (14a) are etched, the bottom portion (B) of the second opening (14b) is removed for exposing the conducting film (12) therein, and the exposed conducting film (12) is etched, so as to form a TFT (20) in a second step. A pixel electrode (5a), a protection masking layer (17a) and a projection (17b) are formed in a third step.

Abstract: An array substrate comprising a base substrate, a common electrode, a gate line, a data line, a thin film transistor, a passivation layer and a pixel electrode of “” shape. The thin film transistor comprises a gate electrode, an active layer, a source electrode and a drain electrode; the gate electrode is connected with the gate line; the source electrode is connected with the data line; and the drain electrode is connected with the pixel electrode. A passivation layer is formed on the source electrode, the drain electrode and the data line, and a via hole is formed in the passivation layer over the drain electrode. The pixel electrode of “” shape is formed on the passivation layer and connected with the drain electrode through the via hole in the passivation layer. The data line is provided below the position corresponding to the boundary between the “/” portion and the “\” portion of the pixel electrode of “” shape. The array substrate increases the transmittivity of pixel and improves the display quality.

Abstract: Disclosed herein is a semiconductor device manufacturing method for performing an annealing process of irradiating a semiconductor film on which element forming areas including thin film transistor forming areas are arranged in a two-dimensional pattern with energy beams using a plurality of irradiating optical systems, wherein in the annealing process, an area irradiated with the energy beams is divided into a single beam irradiated area irradiated by each of the plurality of irradiating optical systems with an energy beam singly and a boundary area situated between single beam irradiated areas adjacent to each other and irradiated by both of two irradiating optical systems performing beam irradiation of the single beam irradiated areas with energy beams.

Abstract: A light emitting diode packaging device includes: a heat dissipating base; a light emitting dice mounted on the heat dissipating base; a lead frame coupled electrically to the light emitting dice and having a protruding wall defining a confining space for extension of a protruding part of the heat dissipating base therethrough; at least one retaining member provided on one of the protruding part of the heat dissipating base and the protruding wall of the lead frame to retain the lead frame to the heat dissipating base; and a molding material molded on the heat dissipating base and the lead frame.

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer.

Abstract: A backside illuminated image sensor comprises a sensor layer implementing a plurality of photosensitive elements of a pixel array, and an oxide layer adjacent a backside surface of the sensor layer. The sensor layer comprises a seed layer and an epitaxial layer formed over the seed layer, with the seed layer having a cross-sectional doping profile in which a designated dopant is substantially confined to a pixel array area of the sensor layer. The doping profile advantageously reduces dark current generated at an interface between the sensor layer and the oxide layer. The image sensor may be implemented in a digital camera or other type of digital imaging device.

Abstract: A thin film transistor array panel is provided, which includes: a semiconductor layer; a first insulating layer on the semiconductor layer; a gate line including a first amorphous silicon layer and a metal; a second insulating layer covering the gate line; and a data line formed on the second insulating layer. A variously tapered structure of the signal line may be formed by providing an amorphous silicon layer having good adhesion characteristics. The adhesion between the metal layer and the amorphous silicon layer may be improved by performing a thermal treatment process such that the contact resistance may be reduced therebetween. Accordingly, the characteristics and reliability of the TFT may be improved.

Abstract: There is provided a wiring substrate. The wiring substrate includes: a semiconductor substrate having a through hole; an insulating film provided to cover an upper surface, a lower surface and a first surface of the semiconductor substrate, the first surface corresponding to a side surface of the through hole; a through electrode provided in the through hole; a first wiring pattern disposed on an upper surface side of the semiconductor substrate and coupled to the through electrode; and a second wiring pattern disposed on a lower surface side of the semiconductor substrate and coupled to the through electrode. A first air gap is provided between the first wiring pattern and the insulating film formed on the upper surface, and a second air gap is provided between the second wiring pattern and the insulating film formed on the lower surface.

Abstract: In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions.

Abstract: A quantum dot electroluminescence device and a method of fabricating the same are provided. The quantum dot electroluminescence device comprises an insulating substrate; a quantum dot luminescence layer supported by the insulating substrate, and composed of a monolayer or multilayer of quantum dots, which are cross-linked by a cross-link agent; an anode electrode and a cathode electrode connected to an external power supply to inject carriers to the quantum dot luminescence layer; a hole transfer layer interposed between the anode electrode and the quantum dot luminescence layer, and composed of p-type polymer semiconductor; and an electron transfer layer interposed between the cathode electrode and the quantum dot luminescence layer, and composed of metal oxide or n-type polymer semiconductor.

Abstract: The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region.

Abstract: A method of forming a fine particle pattern, includes: forming a layer containing a silane coupling agent having a thiol group, an amino group, a hydroxyl group, a carboxyl group, or a sulfo group, each of which is protected by a photolytic protective group on a top-most surface of a substrate; exposing the substrate to light in a pattern; immersing the substrate into a colloidal solution in which metal atom-containing fine particles are dispersed; and allowing the metal atom-containing fine particles to selectively adhere onto an exposed area.