Abstract: Disclosed is a stacked variable inductors manufactured by stacking M (M?2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N?M) metal layers that are different each other; first and second ports each connected to the highest positioned inductor and to the lowest positioned inductor among said 1 to N inductors; and at least one MOSFET, and wherein one terminal of at least one MOSFET is connected to one of the first and second ports, and the other one is connected to one of adjacent terminals connected in serial between 1 to N inductors.

Abstract: A precursor source mixture useful for CVD or ALD of a film comprising: at least one precursor composed of an element selected from the group consisting of Li, Na, K, Rb, Cs, Fr, Be, Mg, Ti, Zr, Hf, Sc, Y, La, V, Nb, Ta, Cr, Mo, W, Mn, Re, Fe, Ru, Os, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Hg, B, Al, Ga, In, Tl, Si, Ge, Sn, Pb, As, P, Sb and Bi, to which is bound at least one ligand selected from the group consisting of hydride, alkyl, alkenyl, cycloalkenyl, aryl, alkyne, carbonyl, amido, imido, hydrazido, phosphido, nitrosyl, nitryl, nitrate, nitrile, halide, azide, alkoxy, siloxy, silyl, and halogenated, sulfonated or silyated derivatives thereof, which is dissolved, emulsified or suspended in an inert liquid selected from the group consisting of aliphatic hydrocarbons, aromatic hydrocarbons, alcohols, ethers, aldehydes, ketones, acids, phenols, esters, amines, alkylnitrile, halogenated hydrocarbons, silyated hydrocarbons, thioethers, amines, cyanates, isocyanates, thiocyanates, silicone oils, nitroalky

Abstract: A variable capacitance formed in a semiconductor substrate with a ribbed surface, having a first electrode formed of all the ribs protruding from the substrate, of portions of the substrate underlying the ribs, and of at least portions of the substrate separating the bases of two ribs, having a second electrode superposed to at least one portion of the first electrode. The ribs are irregular in terms of cross-section and/or planar base surface area.

Abstract: A high-voltage MOS transistor capable of lowering the maximum substrate current without sacrificing the driving capacity of the transistor itself, and ensuring an acceptable lifetime of hot carriers is provided. By providing an overlapping region in a boundary region between a gate electrode and a lightly doped n-type diffusion layer of a drain electrode, it becomes possible to increase by about 50% a dopant dose of the lightly doped n-type diffusion layer, having effects on the so-called transistor characteristic of the n-channel high-voltage MOS transistor described above. Furthermore, by setting an overlapping amount to not less than 0.5 ?m, it becomes possible to create a stable region with maximum substrate current (Isub max.) at not larger than 5 ?A/?m.

Abstract: An integrated circuit package with lead fingers with a footprint on the order of the integrated circuit footprint is provided. A lead frame may be made from a metal sheet, which may be stamped or etched. The lead frame provides a plurality of posts and a connecting sheet connecting the plurality of posts. Dice are adhesively mounted to the plurality of posts. The dice have a conductive side with a plurality of conducting pads where each conducting pad is electrically and mechanically connected to a post. An encapsulating material is placed over the dice and lead frame, with the connecting sheet keeping the encapsulating material on one side of the lead frame. Parts of the connecting sheet are then removed, electrically isolating the posts. The integrated circuit packages formed by the encapsulated dice and leads may be tested as a panel, before the integrated circuit packages are singulated.

Abstract: A semiconductor device has: a wiring board that includes an insulating substrate and a wiring provided on the insulating substrate; a semiconductor chip that is mounted on the wiring board; an opening that is formed at a predetermined position in the insulating substrate, one end of the opening being shut by the wiring to form the bottom of the opening; a thin film conductor that is formed on the surface of the wiring and at the bottom of the opening; an embedded conductor layer that is provided in the opening while contacting the thin film conductor formed at the bottom of the opening; and an external connection terminal that is disposed at the other end of the opening to electrically connect with the wiring through the embedded conductor layer and the thin film conductor provided in the opening.

Abstract: A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

Abstract: In some embodiments, a fabrication method comprises: forming a structure that has one or more substrates, wherein the one or more substrates are either a single substrate or a plurality of substrates bonded together, wherein the structure comprises a non-electronically-functioning component which includes at least a portion of the one or more substrates and/or is attached to the one or more substrates; wherein the one or more substrates include a first substrate which has: a first side, an opening in the first side, and a conductor in the opening; wherein the method comprises removing material from the structure so that the conductor becomes exposed on a second side of the first substrate. In some embodiments, the second side is a backside of the first substrate, and the exposed conductor provides backside contact pads.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.

Abstract: A semiconductor structure for high frequency operation has a substrate with a doped well formed therein and a buffer layer made of a substrate material covers the well. The buffer layer is made of an undoped material and is disposed on a top side of the well for inhibiting an outdiffusion of a dopant from the well. At least a portion of the substrate is not covered by the buffer layer.

Abstract: A vertical or lateral semiconductor component derives a signal from a high load voltage. This signal can be used directly for driving the semiconductor component or, alternatively, a control device.

Abstract: A high-frequency package comprises a dielectric substrate, on an upper face of which a mounting portion of a high-frequency circuit component is formed, a first line conductor formed on the upper face for transmitting high-frequency signals, a first coplanar grounding conductor, a second line conductor formed on a lower face, a second coplanar grounding conductor, a through conductor formed inside for connecting the first and second line conductors, a grounding through conductor connecting the first and second coplanar grounding conductors, a metal terminal bonded to the second line conductor, and grounding metal terminals bonded to the second coplanar grounding conductor, wherein a gap between the grounding metal terminals is equal to or less than ½ of a wavelength of high-frequency signals.

Abstract: High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Abstract: A power device includes a gate electrode, a source electrode, and a drain electrode provided within an active region of a semiconductor substrate of first conductivity type. A vertical diffusion region of second conductivity is provided at a periphery the active region. The vertical diffusion region extends continuously from a top surface of the substrate to a bottom surface of the substrate. The vertical diffusion region includes an upper portion having a first depth and a lower portion having a second depth that is substantially greater than the first depth.

Abstract: An emissive display system includes a matrix of pixels. The matrix of pixels can be comprised of two or more elements. The two or more elements have different areas from each other. The different areas allow the elements to be driven at similar or preferred drive biases and energies despite the different materials utilized to manufacture the elements.

Abstract: A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

Abstract: Structures and methods involve dynamic enhancement mode p-channel flash memories with ultrathin tunnel oxide thicknesses. Both write and erase operations are performed by tunneling. The p-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will now be orders of magnitude faster than traditional p-channel flash memory. Structures and methods for p-channel floating gate transistors are provided that avoid p-channel threshold voltage shifts and achieve source side tunneling erase. The p-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms. The methods further include reading the p-channel memory cell by applying a potential to a control gate of the p-channel memory cell of less than 1.0 Volt.

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract: A microelectromechanical system may be enclosed in a hermetic cavity defined by joined, first and second semiconductor structures. The joined structures may be sealed by a solder sealing ring, which extends completely around the cavity. One of the semiconductor structures may have the system formed thereon and an open area may be formed underneath said system. That open area may be formed from the underside of the structure and may be closed by covering with a suitable film in one embodiment.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: The invention relates to negative photosensitized sheet constructions which, upon exposure to an actinic radiation source through a screened image, can accurately reproduce said image. The construction is useful as a color proofing film which can be employed to predict the image quality from a lithographic printing process.