Abstract: A semiconductor memory capable of attaining a low voltage, a high-speed operation, low power consumption and a high degree of integration is obtained. This semiconductor memory comprises a floating gate electrode, a first source/drain region having a diode structure employed for controlling the potential of the floating gate electrode and a second source/drain region formed to hold a channel region between the same and the first source/drain region. Thus, when a channel of a transistor is turned on in reading, a large amount of current flows from the first source/drain region having a diode structure to a substrate, whereby high-speed reading can be implemented. Further, a negative voltage is readily applied to the first source/drain region having a diode structure, whereby a low voltage and low power consumption are attained and the scale of a step-up circuit is reduced, and hence a high degree of integration can be attained.

Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).

Abstract: The invention includes methods of forming capacitors and capacitor constructions. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. A first layer of a first capacitor dielectric material is formed over the first capacitor electrode. A second layer of the first capacitor dielectric material is formed on the first layer. A second capacitor electrode is formed over the second layer of the first capacitor dielectric material. A capacitor in accordance with an implementation of the invention includes a pair of capacitor electrodes having capacitor dielectric material therebetween comprising a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same capacitor dielectric material.

Abstract: A laminate multilayer ball-grid-array package is suitable for millimeter-wave circuits. The frequency bandwidth of the package is DC to 40 GHz. The package is made using laminate circuit board materials to match the temperature expansion coefficients of the package to the host PCB. Electrical connection between the package and the host PCB on which the package is mounted is achieved using ball-grid-array technology. The package can be sealed, covered, or encapsulated, and is suitable for high-volume production.

Abstract: A semiconductor element has a semiconductor body of a first conductivity type. The semiconductor body has a zone of a second conductivity type embedded. Further regions of the second conductivity type surround the zone of the second conductivity type like a well. The further regions are interrupted in at least one location by a channel that is formed by the semiconductor body. The further regions are doped with a doping concentration that is high enough so that the further regions are not completely depleted of charge carriers when the semiconductor element is revere-biased.

Abstract: In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).

Abstract: In a nitride semiconductor light emitting device chip, a mask pattern on a nitride semiconductor substrate (101) is formed of a growth inhibiting film on which a nitride semiconductor layer is hard to grow. There are a plurality of windows unprovided with the growth inhibiting film. There are at least two different widths as mask widths each between the adjacent windows. The mask pattern includes a mask A group (MAG) and mask B groups (MBG) arranged on respective sides of the mask A group. A mask A width in the mask A group is wider than a mask B width in the mask B group. The nitride semiconductor light emitting device chip further includes a nitride semiconductor underlayer (102) covering the windows and the mask pattern, and a light emitting device structure having a light emitting layer (106) including at least one quantum well layer between an n type layer (103-105) and a p type layer (107-110) over the underlayer.

Abstract: Dielectric rings to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the rings on semiconductor devices and other substrates are disclosed. One or more of the rings may be positioned around the contact pads of a semiconductor device or other substrate before or after solder balls are secured to the contact pads. Upon reflowing the solder balls to connect the semiconductor device face-down to a higher level substrate, the rings prevent the reflowed solder from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures which are attached to a surface of a semiconductor device or other substrate. Alternatively, the rings can be fabricated on the surface of the semiconductor device or other substrate. A stereolithographic method of fabricating the rings is disclosed.

Abstract: A write word line is disposed right under an MTJ element. The write word line extends in an X direction, and a lower surface of the line is coated with a yoke material which has a high permeability. A data selection line (read/write bit line) is disposed right on the MTJ element. A data selection line extends in a Y direction intersecting with the X direction, and an upper surface of the line is coated with the yoke material which has the high permeability. At a write operation time, a magnetic field generated by a write current flowing through a write word line B and data selection line functions on the MTJ element by the yoke material with good efficiency.

Abstract: An inductance integrated in a monolithic circuit, including a conductive spiral having an internal end connected to a connection track, the spiral and the connection track belonging to a same metallization level, in which the connection between the internal end of the spiral and the connection track is formed by a connecting track belonging to a metallization level higher than the metallization level of the spiral.

Abstract: A field emission device, which among other things may be used within an ultra-high density storage system, is disclosed. The emitter device includes an emitter electrode, an extractor electrode, and a solid-state field controlled emitter that utilizes a Schottky metal-semiconductor junction or barrier. The Schottky metal-semiconductor barrier is formed on the emitter electrode and electrically couples with the extractor electrode such that when an electric potential is placed between the emitter electrode and the extractor electrode, a field emission of electrons is generated from an exposed surface of the semiconductor layer. Further, the Schottky metal may be selected from typical conducting layers such as platinum, gold, silver, or a conductive semiconductor layer that is able to provide a high electron pool at the barrier.

Abstract: Electrodes of one face of a semiconductor, which has electrodes formed on both faces, and a heat radiating plate are directly joined to quickly absorb and diffuse heat of the semiconductor, thereby improving a heat radiation effect. At the same time, electrodes on an opposite face of the semiconductor are connected to pillared electrodes that are thicker than a wire for wire bonding and larger in current capacity. These pillared electrodes can accordingly be utilized as connecting terminals to a circuit board. Ceramic is used for the heat radiating plate, so that semiconductors of different functions can be mounted simultaneously.

Abstract: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layer and capacitor dielectric layers in various integrated circuit devices.

Abstract: A semiconductor device in which an electrode is not allowed to easily deform even when a heat treatment is performed on a material forming the electrode during a damascene process for forming a stacked capacitor, and a manufacturing method thereof are provided. A conductive film 5 made of the same material as that of a capacitor lower electrode 6 is formed so as to be adhered to a top face of a conductive film 4 by a heat treatment. If the lower electrode 6 is made of a noble metal such as ruthenium, for example, the conductive film 5 is made of the same noble metal. Because of use of the same material for forming the conductive film 5 and the lower electrode 6, connection between the conductive film 5 and the lower electrode 6 is strengthened. Accordingly, it is easy to maintain connection between the conductive film 5 and the lower electrode 6 during a heat treatment on the lower electrode 6, so that the lower electrode is not likely to deform.

Abstract: A semiconductor package has a substrate comprising a thermosetting resin layer of an approximate planar plate, a plurality of copper patterns formed at top and bottom surfaces of the resin layer, and protective layers coated on predetermined regions of the copper patterns and the thermosetting layer and having a same height at a surface of the resin layer. A semiconductor die is coupled to a center of the top surface of the substrate. A plurality of conductive wires for electrically coupling the semiconductor die to the copper patterns is positioned at the top surface of the resin layer. An encapsulant is used for covering the semiconductor die located at the top surface of the substrate and the conductive wires in order to protect them from the external environment. A plurality of solder balls is coupled to the bottom surface of the substrate.

Abstract: A barrier layer made of AlxGa1-xN (0<x?0.18) is formed in a light-emitting semiconductor device using gallium nitride compound having a multi quantum-well (MQW) structure. By controlling a composition ratio x of aluminum (Al) or thickness of the barrier layer, luminous intensity of the device is improved. An n-cladding layer made of AlxGa1-xN (0<x?0.06) is formed in a light-emitting semiconductor device using gallium nitride compound. By controlling a composition ratio x of aluminum or thickness of the n-cladding layer, luminous intensity of the device is improved. A p-type layer and an n-type layer are formed in a light-emitting semiconductor device using gallium nitride compound having a double-hetero junction structure. By controlling a ratio of a hole concentration of the p-type layer and an electron concentration of the n-type layer approximates to 1, luminous intensity of the device is improved.

Abstract: A semiconductor device has thin film resistors connected in series to form a bleeder resistance circuit. Each of the thin film resistors is made of a polysilicon film doped with B or BF2 P-type impurities and has two end portions each having a high impurity concentration region. A first insulating film overlies the thin film resistors. First conductors are connected to the ends of the thin film resistors for connecting the thin film resistors in series. The semiconductor device has second conductors each connected to a respective one of the first conductors and overlying a respective one of the thin film resistors through the first insulating film.

Abstract: An alloy type thermal fuse is provided in which, although a fuse element essentially comprising an In-Sn alloy is used, the operation stability to a heat cycle can be satisfactorily assured, and, even when the amount of In is large, a process of drawing to the fuse element at a high yield can be ensured, and which has an operating temperature belonging to the range of 120 to 150° C. The fuse element has an alloy composition in which 0.1 to 7 weight parts of one, or two or more metals selected from the group consisting of Ag, Au, Cu, Ni, Pd, Pt, and Sb are added to 100 weight parts of an alloy of 52 to 85% In and a balance Sn.

Abstract: Disclosed is a PIN photodiode used for a light-receiving element for optical communication. The PIN photodiode comprises a gate electrode structure consisting of a gate insulation layer and a gate electrode pad which prevent a bonding layer from being excessively depleted in the lateral direction at the time of applying a negative electric voltage to an electrode that is in contact with the bonding layer. The PIN photodiode allows the control of the electrostatic capacitance of the element by controlling the depletion level of the bonding layer in the lateral direction using the gate electrode pad. Therefore, it is possible to suppress the increase of the electrostatic capacitance and to achieve a high-speed operating property.

Abstract: The present invention is a power semiconductor switch having a monolithically integrated low-voltage lateral junction field effect transistor (LJFET) controlling a high-voltage vertical junction field effect transistor (VJFET). The low-voltage LJFET conducting channel is double-gated by p+n junctions at opposite sides of the lateral channel. A buried p-type epitaxial layer forms one of the two p+n junction gates. A p+ region created by ion implantation serves as the p+ region for the second p+n junction gate. Both gates are electrically connected by a p+ tub implantation. The vertical channel of the vertical JFET is formed by converting part of the buried p-type epitaxial layer into n+ channel via n-type ion implantation.