Abstract: An active matrix organic electroluminescent display device of the present invention is fabricated through a six-mask process unlike the related art that uses eight masks. In the present invention, since the ground line and the power line are entirely or over substantially disposed above the substrate, the resistance of the power line is reduced and thermal damage that may occur in the power line during driving the device is prevented. Therefore, the image quality increases and the uniformity in the display can be obtained. Furthermore, due to the reduction of the mask process, the occurrence of defects is reduced and the production yield can be raised. Additionally, the principle of the present invention can be applied to either the top emission type organic electroluminescent display device or the bottom emission type organic electroluminescent display device. When it is utilized for the top emission type, the active matrix organic electroluminescent display device can have a high aperture ratio.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: The integrated circuit (10) has a substrate and a memory with a first memory unit (30) containing organic material. The first memory unit (30) has a first (26) and a second electrode (28), which are in the non-programmed state electrically connected by an interconnection (27). On programming, the interconnection (27) is at least partially broken in that it is locally heated. This heating can be effected electrically and optically. By preference the first memory unit (30) is integrated in a first layer (6) of organic material, which also has a first electrode (25) of the integrated circuit (10). The integrated circuit (10) can be used in a transponder which is electrically programmable. In the method of programming, the local heating is effected electrically, by applying a voltage across the first memory unit (30).

Abstract: Disclosed is a semiconductor chip mounting substrate 4a bearing semiconductor chips 19a and 19b thereof. The first substrate 4a includes a power source line 22 for supplying a supply voltage potential to the semiconductor chips 19a and 19b, a ground line 23 for supplying a ground voltage potential to the semiconductor chips 19a and 19b, output lines 21a and 21b to which an output signal is supplied from the semiconductor chips 19a and 19b, and an insulator layer 11 for covering the output lines 21a and 21b. The insulator layer 11 is formed so that no insulator layer is arranged in the area between the power source line 22 and the ground line 23.

Abstract: A field emission device, which among other things may be used within an ultra-high density storage system, is disclosed. The emitter device includes an emitter electrode, an extractor electrode, and a solid-state field controlled emitter that utilizes a Schottky metal-semiconductor junction or barrier. The Schottky metal-semiconductor barrier is formed on the emitter electrode and electrically couples with the extractor electrode such that when an electric potential is placed between the emitter electrode and the extractor electrode, a field emission of electrons is generated from an exposed surface of the semiconductor layer. Further, the Schottky metal may be selected from typical conducting layers such as platinum, gold, silver, or a conductive semiconductor layer that is able to provide a high electron pool at the barrier.

Abstract: In a semiconductor heterojunction corresponding to the n-channel and p-channel, the present invention is to enable the selective carrier injection into each channel by employing a height difference of a Schottky barrier, &phgr; B, which is provided between a source/drain consisting of metal or semiconductor-intermetallic compound and a semiconductor film used for each channel of the semiconductor.

Abstract: The present invention is a method and apparatus for a very low profile ball grid array package. A substrate is provided with an aperture. A thin sheet material is secured to the substrate, covering the aperture, so as to form a cavity. A semiconductor die is mounted in the formed cavity on the thin sheet material. The semiconductor die is encapsulated with the thin sheet material supporting it during encapsulation. The use of the thin sheet material to form the cavity is a cost effective way to construct a ball grid array package having a very low profile.

Abstract: A semiconductor device having a photo diode which has substantially the same sensitivity to a plurality of light having different wavelengths, includes a first and a second conductivity type semiconductor layer formed at a surface layer portion of the first conductivity type semiconductor layer, wherein the sensitivity to light of a first wavelength and a second wavelength which is different from the first wavelength, are made substantially the same by designing a region in which a depletion layer spreads from a junction of the first and second conductivity type semiconductor layers and when an inverse bias is applied to the first and second conductivity type semiconductor layers, for example, by designing it to spread in a region of 3 to 6 &mgr;m or a region of 2 to 7 &mgr;m from the surface of the second conductivity type semiconductor layer in the depth direction.

Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.

Abstract: Light emitting diodes are provided with electrode and pad structures which redirect light which otherwise would be blocked by the pad. The LED may be formed as a die with first and second contact surfaces. A pad is in contact with the first contact surface. A reflector is disposed beneath the first pad, and the reflector includes walls that are oblique with respect to the first contact surface.

Abstract: A semiconductor device having a semiconductor chip, a wiring board joined to one surface of the semiconductor chip and electrically connected to the semiconductor chip, and a warp preventing board joined to the other surface of the semiconductor chip and composed of the same material as that of the wiring board. An external connection member for surface mounting may be arranged on a surface, facing away from the semiconductor chip, of the wiring board.

Abstract: A semiconductor-on-insulator (SOI) device. The SOi device includes a substrate, an insulator layer disposed on the substrate and an active region disposed on the insulator layer. The active region includes a source, a drain, and a body disposed therebetween. The source and body form an abrupt or hyperabrupt source/body junction. A gate is disposed on the body to operatively form a transistor. An implanted region forms an interface between the body and the drain, the implanted region formed by tilted atom implantation in a direction towards the active region and under the gate from an angle tilted towards the drain with respect to vertical, the implanted region resulting in the formation of a graded drain/body junction. Also disclosed is a method of fabricating the SOI device.

Abstract: A substrate and method of encapsulating a substrate based electronic package using injection molding and a two piece mold is described. The substrate has a barrier material formed on a gating region of the substrate. The barrier material can be formed directly over circuit wiring traces formed on the substrate thereby avoiding restrictions on the location of circuit wiring traces. The barrier material and encapsulant are chosen such that the adhesive force between the barrier material and the encapsulant is greater than the adhesive force between the barrier material and the substrate. When the mold runner is broken away the barrier material is also peeled away without damage to the substrate or circuit wiring traces.

Abstract: Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two sides, and two ends; and a conductive inhibitor strip that adjoins a portion of one of the two sides of the p-type strip and a portion of one of the two sides of the n-type strip so as to inhibit cross-diffusion between the p-type strip and the n-type strip while electrical connection between n-type and p-type polycrystalline silicon is maintained.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a main surface and a plurality of transistors formed on the main surface. The transistors each include a gate electrode, a diffusion layer formed adjacent to the gate electrode and contacts communicating with the diffusion layer. The contacts corresponding to the transistors include a contact having a first distance from the gate electrode and a contact having a second distance from the gate electrode that is longer than the first distance.

Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.

Abstract: An emitter has an electron supply layer and a silicon-based dielectric layer formed on the electron supply layer. The silicon-based dielectric layer is preferably less than about 500 Angstroms. Optionally, an insulator layer is formed on the electron supply layer and has openings defined within which the silicon-based dielectric layer is formed. A cathode layer is formed on the silicon-based dielectric layer to provide a surface for energy emissions of electrons and/or photons. Preferably, the emitter is subjected to an annealing process thereby increasing the supply of electrons tunneled from the electron supply layer to the cathode layer.

Abstract: A silicon substrate has area-selectively formed porous silicon in which porosity, pore size, and pore size distribution of a porous silicon region and a shape of the porous silicon are controlled. In a silicon forming method of immersing the silicon substrate coated with a mask layer having an opening area into a solution to which forming current is applied, and anodically forming a part of the silicon substrate from the opening area of the mask layer so as to form a porous silicon area in the silicon substrate, the forming current is increased according to degree of growth of the porous silicon such that the interface current density between a growing end part of the porous silicon and silicon substrate in the anodizing process may be substantially kept at constant.

Abstract: An integrated electronic device includes a semiconductor substrate layer having a major surface formed along a crystal plane. In one embodiment a first conductivity type region is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited thereon. The deposited layer includes a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first region form a pn junction. An upper-most substrate surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. Electrical connection is provided to the first doped region with a conductor formed between the first and second planes.

Abstract: First wirings are disposed along a straight line in one row or one column of memory cell arrays. A second wiring is disposed above the first wirings and transmits a signal from one end of the second wiring to the other end thereof. Contact plugs connect the first wirings and the second wiring to each other. The first wirings are connected to a plurality of successive memory cells among all the memory cells in the row or column to which the first wirings belong. In case such an LSI is manufactured and defect analysis is made to thereby form an FBM, it is decided that the contact plugs connecting the first wirings to the second wiring are disconnected when a plurality of successive memory cells in one row or one column. Thus, a plurality of defects are expressed by the use of different categories.