Patents Examined by Kripa Sagar
  • Patent number: 6830875
    Abstract: A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: December 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Stephen J. Fuerniss, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
  • Patent number: 6824931
    Abstract: A verification photomask disclosed. The mask may be for process window verification purposes when switching between fabrication equipment, and/or for optical proximity correction (OPC) verification purposes. The mask includes device areas that are separated by scribe lines. One or more verification patterns are integrated into the scribe lines for verification purposes. These patterns can include: proximity patterns, photoresist-spacing patterns, polysilicon end cap patterns, as well as other patterns. A method for making the mask, and a semiconductor device created at least in part by a method including use of the mask, are also disclosed.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: November 30, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Kun-Yi Liu, Ching-Ming Chen, Chin-Chuan Hsieh
  • Patent number: 6818389
    Abstract: A circuit fabrication and lithography process utilizes a mask including dense repetitive structures of features that result in a wide array of fine densely populated features on the exposed substrate film. Following this, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate. An optional final step adds additional features as well as the interconnect features thus forming a circuit pattern. In this manner, all fine features may be generated using the exact same density of intensity patterns, and therefore, maximum consistency between features is established without the need for optical proximity correction.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: November 16, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Michael Fritze, Brian Tyrrell
  • Patent number: 6811959
    Abstract: A process for manufacturing and a photomask including a chrome layer over a transparent substrate, followed by a thin hardmask/barrier layer directly over the chrome layer having a thin resist layer thereover. The thin resist layer is patterned and developed wherein the barrier layer acts to retard the formation of a resist “foot” at the bottom of the resist profile. Exposed portions of the hardmask/barrier layer and the underlying chrome layer are etched, and then any remaining hardmask/barrier layer and resist layer is subsequently removed by an etchant. The hardmask/barrier layer directly over the chrome layer enables an improved pattern transfer mask during chrome etching processes, allows for further reduction in the thickness of the resist layer, improves the image quality, the achievable minimum resolution features, and provides nominal image size control and image size uniformity across the photomask within current process flows and manufacturing.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: November 2, 2004
    Assignee: International Business Machines Corporation
    Inventor: Christopher K. Magg
  • Patent number: 6811945
    Abstract: A method of producing a pattern-formed structure, comprising: preparing a substrate for a pattern-formed structure having a characteristic-modifiable layer whose characteristic at a surface thereof can be modified by the action of photocatalyst; preparing a photocatalyst-containing-layer side substrate having a photocatalyst-containing layer formed on a base material, the photocatalyst-containing layer containing photocatalyst, arranging the substrate for a pattern-formed structure and the photocatalyst-containing-Iayer side substrate such that the characteristic-modifiable layer faces the photocatalyst-containing layer with a clearance of no larger than 200 &mgr;m therebetween; and irradiating energy to the characteristic-modifiable layer from a predetermined direction, and modifying characteristic of a surface of the characteristic-modifiable layer, thereby forming a pattern at the characteristic-modifiable layer.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: November 2, 2004
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Hironori Kobayashi
  • Patent number: 6811932
    Abstract: A method and system for determining a mask for fabricating semiconductor device is described. The method and system include patterning a resist layer on at least one mask material to provide a patterned resist layer. The patterned resist layer has a plurality of apertures therein. The plurality of apertures is for the plurality of features. The plurality of apertures has a plurality of apertures sizes and a plurality of aperture pitches. The method and system also include providing a test mask for a plurality of features using the resist layer. The test mask has the plurality of apertures therein. The method and system also include determining a plurality of flow rates for the plurality of aperture pitches and the plurality of aperture sizes based upon the plurality of features.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hung-Eil Kim
  • Patent number: 6806021
    Abstract: Disclosed is a method of forming a pattern comprising coating a solution containing a compound having a silicon-nitrogen linkage in the main chain thereof over a surface of a working film to form a mask, replacing the nitrogen in the mask by oxygen, forming a resist film on a surface of the mask, forming a resist pattern by subjecting the resist film to a patterning exposure and to a developing treatment, transcribing the resist pattern to the mask to form a masking pattern, and transcribing the masking pattern to the working film to form a working film pattern.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: October 19, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Sato, Yasunobu Onishi
  • Patent number: 6803175
    Abstract: A method of producing a pattern-formed structure, comprising: preparing a substrate for a pattern-formed structure having a characteristic-modifiable layer whose characteristic at a surface thereof can be modified by the action of photocatalyst; preparing a photocatalyst-containing-layer side substrate having a photocatalyst-containing layer formed on a base material, the photocatalyst-containing layer containing photocatalyst; arranging the substrate for a pattern-formed structure and the photocatalyst-containing-layer side substrate such that the characteristic-modifiable layer faces the photocatalyst-containing layer with a clearance of no larger than 200 &mgr;m therebetween; and irradiating energy to the characteristic-modifiable layer from a predetermined direction, and modifying characteristic of a surface of the characteristic-modifiable layer, thereby forming a pattern at the characteristic-modifiable layer.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: October 12, 2004
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Hironori Kobayashi
  • Patent number: 6803178
    Abstract: There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: October 12, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Scott A. Bell, Todd P. Lukanc, Marina V. Plat, Uzodinma Okoroanyanwu, Hung-Eli Kim
  • Patent number: 6800405
    Abstract: A method of producing a pattern-formed structure, comprising: preparing a substrate for a pattern-formed structure having a characteristic-modifiable layer whose characteristic at a surface thereof can be modified by the action of photocatalyst; preparing a photocatalyst-containing-layer side substrate having a photocatalyst-containing layer formed on a base material, the photocatalyst-containing layer containing photocatalyst; arranging the substrate for a pattern-formed structure and the photocatalyst-containing-layer side substrate such that the characteristic-modifiable layer faces the photocatalyst-containing layer with a clearance of no larger than 200 &mgr;m therebetween; and irradiating energy to the characteristic-modifiable layer from a predetermined direction, and modifying characteristic of a surface of the characteristic-modifiable layer, thereby forming a pattern at the characteristic-modifiable layer.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: October 5, 2004
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Hironori Kobayashi
  • Patent number: 6800401
    Abstract: A system and method of strong phase-shifting a beam from an actinic light source in a lithographic process includes focusing a beam from the electromagnetic beam source onto a mask adapted to selectively phase-shift at least a portion of the beam according to a predetermined pattern. The beam is passed from the actinic light source through the mask producing a phase-shifted beam, and the phase-shifted beam is directed at a substrate such as a semiconductor wafer adapted to be selectively etched according to the predetermined pattern. The strong phase-shift serves to substantially eliminate zero-order light in the phase-shifted beam. Strong phase-shift mask techniques, through a two electromagnetic beam interference imaging process, are known in the art of microlithography to form imaging results for features of a size well below the limit of conventional prior art imaging.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: October 5, 2004
    Assignee: Petersen Advanced Lithography, Inc.
    Inventor: John S. Petersen
  • Patent number: 6800428
    Abstract: A method of generating an exposure pattern for lithography to create a plurality of patterns arranged in a predetermined direction, comprises a step of counting the plurality of patterns along this predetermined direction, and generating a first enlarged pattern by moving the edges to a first direction along the predetermined direction for a pattern with an odd number, and by moving the edges to a second direction, which is opposite to the first direction, for a pattern with an even number, and a step of generating a second enlarged pattern by moving the edges to the second direction for the pattern with an odd number, and by moving the edges to the first direction for the pattern with an even number. And the first and second patterns are used for creating the plurality of original patterns in a lithography step using the respective enlarged patterns.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: October 5, 2004
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Okada, Taketoshi Omata, Kazuya Sugawa, Kiyokazu Aiso, Masao Sugiyama, Tomoaki Kawaguchi
  • Patent number: 6797456
    Abstract: A method for forming a photoresist structure that does not have swelling defects. A layer of low activation energy deep ultraviolet photoresist is disposed over a layer that is to be patterned. A layer of high activation energy deep ultraviolet photoresist is then deposited such that the layer of high activation energy photoresist directly overlies the layer of low activation energy photoresist. The two photoresist layers are then processed by performing exposure, post-exposure bake, and development steps to form a photoresist structure. An etch step is then performed so as to form a patterned layer that does not have swelling defects.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: September 28, 2004
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yiming Gu, John L. Sturtevant, Anging Zhang
  • Patent number: 6780574
    Abstract: An exposure method in which a multiple exposure process including a first exposure for a first pattern and a second exposure for a second pattern is performed by use of a projection optical system to thereby resolve a desired pattern. The exposure method includes setting a numerical aperture NA1 of the projection optical system for the first pattern exposure and setting a numerical aperture NA2 of the projection optical system for the second pattern exposure to be different from each other.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: August 24, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Miyoko Kawashima
  • Patent number: 6777140
    Abstract: A reflector for EUV has additional multi-layers on the front surface of a base multilayer stack provided selectively to compensate for figure errors in the base multilayer stack or the substrate on which the multilayer stack is provided. A reflective mask for EUV uses two multilayer stacks, one introducing a relative phase shift and/or altered reflectivity with respect to the other one.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: August 17, 2004
    Assignee: ASML Netherlands B.V.
    Inventors: Mandeep Singh, Josephus Johannes Maria Braat
  • Patent number: 6777170
    Abstract: Methods for the preparation of multilayered resists are described. A first layer of photoresist is deposited onto a substrate. First portions of the first layer are exposed to a first dose of radiant energy. A second layer of photoresist is deposited at atop the first layer and second portions of the second layer are exposed to a second varied dose of radiant energy. The dose is modulated over different portions of a layer to preferentially enhance development within the interior of the structure to reduce total development times.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: August 17, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Theodore M. Bloomstein, Roderick R. Kunz, Stephen T. Palmacci
  • Patent number: 6773865
    Abstract: This invention discloses an anti-charging layer for beam lithography and mask fabrication. This invention reduces beam displacement and increases pattern placement accuracy. The process will be used in the beam fabrication of high-resolution lithographic masks as well as beam direct write lithography of electronic devices. The anti-charging layer is formed by the use of metal films bound to metal ligating self-assembled monolayers (SAMs) as discharge layers.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: August 10, 2004
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Elizabeth Dobisz, Walter J. Dressick, Susan L. Brandow, Mu-San Chen
  • Patent number: 6767672
    Abstract: The present invention relates to a method for forming a multi-transmittance phase-shifting mask for the manufacture of highly integrated semiconductor devices in which portions of a plurality of light blocking layers are selectively removed to modify the transmittance of various regions of the mask and suppress undesired patterns, such as ghost images and side lobe effects to permit increased integration levels and improved yield in the production of the semiconductor devices.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: July 27, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Ji-Suk Hong, Hee-Bom Kim, Sang-Sool Koo
  • Patent number: 6767690
    Abstract: The invention encompasses a method for forming a pattern across and expanse of photoresist. The expanse comprises a defined first region, second region and third region. The first region is exposed to a first radiation while leaving the third region not exposed; and subsequently the second region is exposed to a second radiation while leaving the third region not exposed to the second radiation. The second radiation is different from the first radiation. The exposure of the first and second regions in a solvent relative to the solubility of the third region of the expanse. After the first and second regions of the expanse are exposed to the first and second radiations, the expanse is exposed to a solvent to pattern the expanse. The invention can be utilized in forming radiation-patterning tools and stencils; and in patterning semiconductor substrates.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: July 27, 2004
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 6767692
    Abstract: A photoresist-free and ARC-free lip on the periphery of the upper surface of a semiconductor substrate adjacent the end edge of the substrate is formed by the steps of: forming an ARC layer on one surface of a semiconductor substrate; chemically treating the ARC layer to chemically terminate the ARC layer a first distance from the end edge of the substrate; forming a photoresist layer over the semiconductor substrate and over the ARC layer thereon; and exposing the peripheral portion of the photoresist layer to UV light followed by development of the exposed peripheral portion of the photoresist layer to photolithographically terminate the photoresist layer a second distance from the end edge of the substrate wherein the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: July 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Roger Young, Ann Kang, Bruce Whitefield