Patents Examined by Kripa Sagar
  • Patent number: 6610464
    Abstract: A process for patterning a non-rigid membrane in a closed gap environment including the optional step of applying a solvent to the non-rigid membrane, applying a layer of an energy-sensitive composition to the non-rigid membrane, spinning the non-rigid membrane, inverting the non-rigid membrane with the layer of an energy-sensitive composition, spinning the inverted non-rigid membrane, re-inverting the non-rigid membrane, and spinning the re-inverted, non-rigid membrane. As a result of the inverting step and the inverted spinning step, the layer of an energy-sensitive composition does not cause the non-rigid membrane to sag and the resulting layer of energy-sensitive composition is substantially uniform in thickness. The energy-sensitive composition may be a photoresist, such as a chemically amplified photoresist.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: August 26, 2003
    Assignee: Agere Systems Inc.
    Inventor: Leonidas E. Ocola
  • Patent number: 6596444
    Abstract: A method for correcting pattern errors on a photomask is disclosed. The method includes determining a proximity effect caused by a first feature on a second feature in a pattern data file. The total line edge length is calculated for the first feature and a dimension of the second feature is modified based on the total line edge length calculated or the first feature.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: July 22, 2003
    Assignee: DuPont Photomasks, Inc.
    Inventor: Peter Buck
  • Patent number: 6593064
    Abstract: A stepper for imaging integrated circuit and flat panel displays uses a thermoresist instead of photoresist and separates the mask into multiple masks, each one containing only part of the features which need to be imaged. The fmal image is generated by combining the images from all the masks on a single die taking advantage of the fact that thermal resists do not follow the reciprocity law. For maximum resolution each one of the multiple masks contains features of only one size.
    Type: Grant
    Filed: October 13, 2000
    Date of Patent: July 15, 2003
    Assignee: Creo Inc.
    Inventor: Daniel Gelbart
  • Patent number: 6589711
    Abstract: There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: July 8, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Christopher F. Lyons, Marina V. Plat, Bhanwar Singh
  • Patent number: 6586158
    Abstract: This invention discloses an anti-charging layer for beam lithography and mask fabrication. This invention reduces beam displacement and increases pattern placement accuracy. The process will be used in the beam fabrication of high-resolution lithographic masks as well as beam direct write lithography of electronic devices. The anti-charging layer is formed by the use of metal films bound to metal ligating self-assembled monolayers (SAMs) as discharge layers.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: July 1, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Elizabeth Dobisz, Walter J. Dressick, Susan L. Brandow, Mu-San Chen
  • Patent number: 6582889
    Abstract: A two layer structure resist pattern with a T-shaped cross section, consisting of a lower layer and an upper layer with overhang portions is formed, and then the formed two layer structure resist pattern is heat-treated so that the overhang portions of the upper layer incline downward.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: June 24, 2003
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Patent number: 6582890
    Abstract: The invention relates to a multilayer microstructure and a method for preparing thereof. The method involves first applying a first photodefinable composition having a first exposure wavelength on a substrate to form a first polymeric layer. A portion of the first photodefinable composition is then exposed to electromagnetic radiation of the first exposure wavelength to form a first pattern in the first polymeric layer. After exposing the first polymeric layer, a second photodefinable composition having a second exposure wavelength is applied on the first polymeric layer to form a second polymeric layer. A portion of the second photodefinable composition is then exposed to electromagnetic radiation of the second exposure wavelength to form a second pattern in the second polymeric layer. In addition, a portion of each layer is removed according to the patterns to form a multilayer microstructure having a cavity having a shape that corresponds to the portions removed.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: June 24, 2003
    Assignee: Sandia Corporation
    Inventors: Paul Michael Dentinger, Karen Lee Krafcik
  • Patent number: 6576403
    Abstract: A method for forming a thin film transistor with lightly doped drain structure comprising the steps of forming a gate insulating layer and a gate electrode on a polysilicon layer; forming a photoresist layer with a predetermined thickness on the gate electrode and on a portion of the polysilicon layer; and implanting first conductive type impurities into the polysilicon layer so as to form a first ion-implant region and a second ion-implant region, wherein the doping concentration of the second ion-implant region is higher than that of the first ion-implant region.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 10, 2003
    Assignee: Hannstar Display Corporation
    Inventors: Ji-ho Kung, Chih-chang Chen
  • Patent number: 6576402
    Abstract: A metal layer, an etching resist and a photoresist are successively applied to an electrically insulating substrate. Whereupon the photoresist is patterned by photolithography in such a way that it covers a pattern of the later coarse conductor structures and the entire region of the later fine conductor structures. After the uncovered etching resist has been stripped, the photoresist is removed, whereupon the etching resist is patterned with the aid of a laser beam in such a way that it has the pattern of the fine conductor structures. The coarse conductor structures and the fine conductor structures are then formed in a common etching process.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: June 10, 2003
    Assignee: Siemens Production & Logistics Systems AG
    Inventors: Marcel Heerman, Eddy Roelants, Jozef Van Puymbroeck
  • Patent number: 6569607
    Abstract: Method of fabricating microstructures on a substrate. The method comprises providing a substrate layer having a first surface with a resist layer. First selected regions of the resist layer are exposed to an environment that renders the resist layer more or less soluble in a developer solution. The resist layer is then developed in the developer solution to expose selected regions of the substrate surface. Second selected regions of the resist layer are then exposed to an environment that renders the resist layer more or less soluble in the developer solution by aligning exposure of the second selected regions to the first selected regions. The first selected regions of the substrate surface are etched. Second selected regions of the resist layer are then developed to expose the second selected regions of the substrate surface.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: May 27, 2003
    Assignee: Caliper Technologies Corp.
    Inventor: Richard J. McReynolds
  • Patent number: 6555296
    Abstract: A fine pitch wafer bumping process comprises: providing a wafer that has a plurality of contact pads exposed by a passivation layer formed on the surface of the wafer, wherein an under bump metal (UBM) is formed respectively on each contact pad; on the surface of the wafer, forming a first mask film having a plurality of first openings that expose respectively the under bump metals (UBM); filling a first solder material respectively in the first openings; reflowing the first solder material into a plurality of solder posts; on the first mask film, forming a second mask film having a plurality of second openings that respectively expose the first openings; filling a second solder material respectively in the second openings; reflowing the second solder material and the first solder posts; removing the first and second mask films; and reflowing the first and second solder posts to form a plurality of bumps.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: April 29, 2003
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Raymond Jao, Eric Ko, Alex Yang
  • Patent number: 6555294
    Abstract: A process for collectively making integrated magnetic heads with a bearing surface obtained by photolithography. According to the process, on a wafer is deposited a plurality of heads, a mask defining the profile of the bearing surfaces and the wafer is collectively engraved in the vicinity of the pole pieces of the heads. Such a process may find particular application to the making of magnetic heads.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: April 29, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Baptiste Albertini, Pierre Gaud, GĂ©rard Barrois, Henri Sibuet
  • Patent number: 6548223
    Abstract: The invention encompasses a method for forming a pattern across an expanse of photoresist. The expanse comprises a defined first region, second region and third region. The first region is exposed to a first radiation while leaving the third region not exposed; and subsequently the second region is exposed to a second radiation while leaving the third region not exposed to the second radiation. The second radiation is different from the first radiation. The exposure of the first and second regions of the expanse to the first and second radiations alters the solubility of the first and second regions in a solvent relative to the solubility of the third region of the expanse. After the first and second regions of the expanse are exposed to the first and second radiations, the expanse is exposed to a solvent to pattern the expanse. The invention can be utilized in forming radiation-patterning tools and stencils; and in pattering semiconductor substrates.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: April 15, 2003
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 6537732
    Abstract: A resist pattern includes: an upper layer pattern made of a resist; and a lower layer pattern made of a material being soluble in a developer used for forming the upper layer pattern. The upper layer pattern extends over a portion corresponding to a thin-film pattern to be formed and other portions while the lower layer pattern is formed only in the other portions. The lower layer pattern may be made of polymethylglutarimide with or without a dye. The thin-film pattern is formed through any of an etching method, a liftoff method, and a method utilizing both etching and liftoff methods.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: March 25, 2003
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Patent number: 6528238
    Abstract: Groove patterns on substrates coated with photoresist are made using the technique of photolithography by exposing photoresist via a reticle. In the instant invention, the pattern is provided on the reticle with a period larger than the final period to be printed on the photoresist. The complete pattern is obtained by subjecting the photoresist to two or more exposures and aligning the substrate relative to the reticle between exposures. In a further embodiment the slits on the reticle defining the line width of the grooves are larger than required and photoresist is subjected to multiple partial exposure. Both embodiments significantly reduce diffraction caused by the reticle and improve the resolution of the technique.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: March 4, 2003
    Inventors: David Seniuk, Paul J. Paddon, David M. Adams