Patents Examined by Kripa Sagar
  • Patent number: 6759175
    Abstract: An method is disclosed for on-site preparation of a relief image comprising the following steps: (a) laminating a material comprising, in the order given, a first peelable support (1), an image recording layer (2) and an adhesive layer (3) onto a UV-sensitive material comprising a support (7), an UV-sensitive layer (6) wherein the adhesive layer (3) is laminated to the UV-sensitive layer (6); (b) image-wise exposing the image recording layer (2) to form a mask; (c) flood exposing the UV-sensitive material through the mask; (d) developing the UV-sensitive material; wherein the peelable support (1) is removed either before step (b), (c) or (d). Steps (a) to (d) are performed within a period of less than 2 months. As a result the extent of monomer diffusion from the UV-sensitive layer to the image recording layer is reduced. Additionally the adhesion between the image recording layer and the UV-sensitive material is optimised.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 6, 2004
    Assignee: AGFA-Gevaert
    Inventors: Eddie Daems, Luc Leenders
  • Patent number: 6756185
    Abstract: The same mask pattern is used as an etching mask in defining the horizontal location of micro-machined (etched) features at the substrate surface of an optical device relative to the waveguide cores also at the substrate surface of the optical device. Exemplary micro-machined features include grooves, recesses and inclined surfaces formed in the substrate surface for any of a variety of purposes. The accurate horizontal positioning of these features relative to the integrated waveguide cores fosters accurate optical coupling between the integrated waveguide cores and external and/or internal components.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: June 29, 2004
    Assignee: Shipley Company, L.L.C.
    Inventor: Dan A. Steinberg
  • Patent number: 6750000
    Abstract: A method of manufacturing an electron device provided with minute structure such as a semiconductor integrated circuit using projection exposure technique and phase shift mask technique, maintaining a high yield is disclosed. In an electron device manufacturing method according to the invention, a desired electron device is manufactured by printing a light shielding film pattern on a photosensitive film provided on the surface of a workpiece by a projection tool using a mask where a phase shifter having predetermined thickness is partially formed on the flat surface of a transparent plate and a light shielding film having a predetermined pattern and made of non-metal is partially provided with the film covering the end of the shifter and developing the photosensitive film.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: June 15, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Toshihiko Tanaka, Norio Hasegawa, Hiroshi Shiraishi, Hidetoshi Satoh
  • Patent number: 6737224
    Abstract: A method for preparing thin supported films by vacuum is disclosed. The method results in a substrate with windows. The windows are cutout (etched) areas that are covered by a thin film. The method for creating the substrate with thin film covering requires: masking off one surface of the metal substrate with a maskant; placing the metal substrate under a vacuum; treating the unmasked surface by plasma etching; coating the treated surface with a film while still under vacuum; removing substrate from vacuum; remove the masking; treating the previously masked side with photo resist; exposing the side treated with photo resist to artwork of a desired pattern; exposing the substrate to a suitable solution; chemically etching in areas selectively exposed by the artwork; neutralizing the substrate; and removing the etched parts from the substrate.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: May 18, 2004
    Inventor: Jeffrey Stewart
  • Patent number: 6737222
    Abstract: A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: May 18, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Christopher F. Lyons, Marina V. Plat, Scott A. Bell
  • Patent number: 6730444
    Abstract: Needle comb reticle patterns for use in both critical dimension analysis and registration analysis with a registration tool are disclosed. One embodiment of a needle comb reticle pattern includes a box-in-box feature flanked on two adjacent sides by needle combs with tapered flat-tipped needles. Another embodiment of a needle comb reticle pattern includes a box-in-box feature flanked on two adjacent sides by needle combs with tapered flat-tipped needles and flanked on the other two adjacent sides by reference bars. Yet another embodiment of a needle comb reticle pattern includes two complementary needle comb reticle subpatterns, each subpattern including a box-in-box feature with four flanking needle combs. A registration tool can be used with the needle combs and reference bars to measure critical dimension of a semiconductor process. The registration tool can also be used with the box-in-box feature to measure registration between two adjacent layers during semiconductor fabrication.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: May 4, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Steve W. Bowes
  • Patent number: 6727025
    Abstract: A photomask illuminated with an exposure illuminating light having a short wavelength of, e.g., about 200 nm or less and having an improved uniformity of transmittance distribution. On one surface (B) of a flat substrate (1) made of quartz, a quartz glass, or a quartz glass to which a predetermined impurity is added, a thin film (3) made of a material semitrasparent to the exposure illuminating light. The transmittance distribution for the illuminating light of the substrate (1) is measured prior to the formation of the thin film (3), and the distribution of the thickness of the thin film (3) is determined so as to compensate the unevenness of the transmittance distribution. An original pattern (2) is formed on the opposed surface (A) of the substrate (1) to the surface (B).
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: April 27, 2004
    Assignee: Nikon Corporation
    Inventor: Naomasa Shiraishi
  • Patent number: 6723476
    Abstract: The invention includes a method of patterning a mass of material. A beam of activated particles is formed proximate the mass of material, and a pattern of deposit is formed on a surface of the mass with the beam of activated particles. The mass is then etched while using the deposit as an etch mask. The mass of material can be associated with a radiation-patterning tool, such as, for example, a photomask, or can be associated with a semiconductor substrate. The invention also encompasses a photomask construction comprising a substrate, and a patterned material over the substrate. The patterned material covers some regions of the substrate, and leaves other regions not covered. A carbon-containing layer is on the patterned material, but not over the regions of the substrate that are not covered by the patterned material.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: April 20, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Baorui Yang
  • Patent number: 6716571
    Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Calvin T. Gabriel, Harry J. Levinson, Uzodinma Okoroanyanwu
  • Patent number: 6713231
    Abstract: To alleviate the absolute value control accuracy of phases in a mask having a groove shifter structure, transfer regions 4C, 4D formed at different planar positions on the same plane of the same mask 2 are subjected to a multiple exposure by scanning exposure. Although identical mask patterns are formed over the transfer regions 4C, 4D, respective groove shifters 2d provided to these mask patterns are arranged opposite from each other.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: March 30, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Norio Hasegawa, Akira Imai, Katsuya Hayano
  • Patent number: 6709792
    Abstract: A shielding film is formed on the surface of a substrate and a pair of aperture patterns for light transmission with substantially the same line width are formed in the above shielding film so as to run parallel to each other with a gap and to be isolated from other aperture patterns for light transmission. The exposure amount (exposure energy to sufficiently large aperture pattern) at the time a photoresist is exposed by using this photo mask is 4 or more times and 20 or less times as large as the exposure amount on the border where the photoresist is converted from soluble to insoluble through the exposure or the exposure amount on the border from insoluble to soluble. Thereby, it becomes possible to form a microscopic pattern without using an auxiliary pattern method or a phase shift mask and the default inspection of a mask can be made easy.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: March 23, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Shuji Nakao
  • Patent number: 6709806
    Abstract: Disclosed is a method of manufacturing a composite member in which a conductive portion is selectively formed in an insulator. The method comprises the steps of forming a photosensitive composition layer containing a compound forming an ion-exchange group upon irradiation with light having a wavelength not shorter than 280 nm within or on the surface of an insulator, exposing selectively the photosensitive composition layer to light having a wavelength not shorter than 280 nm, forming an ion-exchange group in the exposed portion, and bonding a metal or metal ions to the ion-exchange group formed in the exposed portion of the photosensitive composition layer.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Hotta, Toshiro Hiraoka, Koji Asakawa, Shigeru Matake
  • Patent number: 6706453
    Abstract: A shielding film is formed on the surface of a substrate and a pair of aperture patterns for light transmission with substantially the same line width are formed in the above shielding film so as to run parallel to each other with a gap and to be isolated from other aperture patterns for light transmission. The exposure amount (exposure energy to sufficiently large aperture pattern) at the time a photoresist is exposed by using this photo mask is 4 or more times and 20 or less times as large as the exposure amount on the border where the photoresist is converted from soluble to insoluble through the exposure or the exposure amount on the border from insoluble to soluble. Thereby, it becomes possible to form a microscopic pattern without using an auxiliary pattern method or a phase shift mask and the default inspection of a mask can be made easy.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: March 16, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Shuji Nakao
  • Patent number: 6703168
    Abstract: An isolated light-shielding pattern formed from a light-shielding film region 101 and a phase shift region 102 is formed on a transparent substrate 100 serving as a mask. The phase shift region 102 has a phase difference with respect to a light-transmitting region of the transparent substrate 100. Moreover, the width of the phase shift region 102 is set such that a light-shielding property of the phase shift region 102 becomes at least about the same as that of a light-shielding film having the same width.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: March 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Akio Misaka
  • Patent number: 6692875
    Abstract: A mask contains a transparent carrier material on which an opaque region is disposed as an image structure. Also disposed on the carrier material is a semitransparent dummy structure, which is spaced apart from all the image structures and differs from the image structure in terms of transparency and phase rotation. The smallest lateral extent of the dummy structure is then selected to be at least half as large as the smallest lateral extent of the image structure. The semitransparent dummy structure is formed in such a way that it is suitable for increasing the depth of focus of structures that stand individually or at least partially individually, in order thereby to improve the process window of the optical projection.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: February 17, 2004
    Assignee: Infineon Technologies AG
    Inventors: Werner Fischer, Fritz Gans, Rainer Pforr, Jörg Thiele
  • Patent number: 6692902
    Abstract: A manufacturing method and structure of slanting diffusive reflectors simplifies their manufacturing process and reduces cost. A photo mask comprising a plurality of half-tone exposure units is used. A half-tone photolithography process is performed on the positive photoresist formed on a substrate. Only one exposure process and a suitable drying step are required to form a plurality of slants and rough astigmatisms on the slants. The size of the half-tone exposure units is randomly selected. Each half-tone exposure unit comprises a plurality of parallel transmitting strips or shadow strips. The pitch of the transmitting strips or the shadow strips in one half-tone exposure unit can be arbitrary. The width of the shadow strips is gradually changing from one side of the half-tone exposure unit to the other side.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: February 17, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Chun Wong, Ming-Dar Wei, Shang-Wen Chang
  • Patent number: 6686130
    Abstract: In the light exposure step of the device pattern, the monitor region is exposed to light together with the device region for every chip, and chip {circle around (4)} within the wafer, the chip {circle around (4)} having the focus conditions in the light exposure step close to a set value and having an average value of the dose, is extracted after the light exposure of the device pattern and before the developing treatment. The monitor region arranged within the extracted chip {circle around (4)} is irradiated with light during the development of the resist, and the stopping time of the development for finishing the device pattern in a desired size is estimated on the basis of the change in the intensity of the reflected light of the monitor region. Further, a developing solution is supplied onto the wafer during the estimated stopping time of the development so as to stop the development.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Shinichi Ito
  • Patent number: 6686132
    Abstract: A method for enhancing resist sensitivity and resolution based on influencing the effects of photoacid drift and diffusion by an externally applied electric field that may optionally include a direct current offset bias is disclosed. An electric field applied to the resist film during post exposure bake (PEB) enhances photoacid drift in the direction of the applied electric field, reduces bake time, and results in less undesired diffusion. Electric-field enhanced PEB can reduce PEB time by about 30%, and at the same time, improve the sharpness of 2D corners and increase the verticality of resist sidewalls. Electric-field-enhanced PEB also significantly improves the tolerance of over-exposure and provides better critical dimension control. It is estimated that the lateral acid diffusion length is reduced by about 50%. An apparatus for carrying out the aforementioned method is also provided.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: February 3, 2004
    Assignee: The Regents of the University of California
    Inventors: MoSong Cheng, Andrew R. Neureuther
  • Patent number: 6686102
    Abstract: A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask (25) having chrome regions (22) that define non-critical dimension features (6c) and also serve as protection for phase shift exposure of critical dimension features (6g). The phase shift photomask (23) includes apertures 200, 20&pgr; that expose the sides of the critical dimension feature (6g) with opposite phase light. The phase shift photomask (23) also includes an additional aperture (30) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature (6c) and the end of a critical dimension feature (6g).
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: February 3, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: John N. Randall, Gene E. Fuller
  • Patent number: 6680150
    Abstract: Sidelobe formation in photolithographic patterns is suppressed by non-rectangular, non-circular contact openings formed in attenuated phase shift photomasks. The contact openings may be diamond-shaped, star-shaped, cross-shaped, or various other shapes which include multiple vertices. The contact opening shapes may include only straight line segments or they may include rounded segments. The contact openings may be arranged in various relative configurations such as in arrays in which the contact openings are sized and spaced by sub-wavelength dimensions. A method for forming contact openings on a photosensitive film uses the attenuated phase shift photomask to form a contact pattern free of pattern defects. A computer readable medium includes instructions for causing a photomask manufacturing tool to generate the attenuated phase-shift photomask.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: January 20, 2004
    Assignee: Agere Systems Inc.
    Inventors: James W. Blatchford, Jr., Omkaram Nalamasu, Stanley Pau