Patents Examined by Latanya N Crawford
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Patent number: 11744163Abstract: A spin-orbit-torque type magnetoresistance effect element includes: a first ferromagnetic layer; a second ferromagnetic layer; a non-magnetic layer which is located between the first ferromagnetic layer and the second ferromagnetic layer; and a spin-orbit-torque wiring which has the first ferromagnetic layer laminated thereon, wherein the spin-orbit-torque wiring extends in a second direction intersecting a first direction corresponding to an orthogonal direction of the first ferromagnetic layer, wherein the first ferromagnetic layer includes a first laminated structure and an interface magnetic layer in order from the spin-orbit-torque wiring, wherein the first laminated structure is a structure in which a ferromagnetic conductor layer and an inorganic compound containing layer are disposed in order from the spin-orbit-torque wiring, wherein the ferromagnetic conductor layer contains a ferromagnetic metal element, and wherein the inorganic compound containing layer contains at least one inorganic compound seType: GrantFiled: July 22, 2020Date of Patent: August 29, 2023Assignee: TDK CORPORATIONInventor: Yohei Shiokawa
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Patent number: 11730064Abstract: A magnetic memory device including a lower electrode on a substrate; a conductive line on the lower electrode; and a magnetic tunnel junction pattern on the conductive line, wherein the conductive line includes a first conductive line adjacent to the magnetic tunnel junction pattern; a second conductive line between the lower electrode and the first conductive line; and a high resistance layer at least partially between the first conductive line and the second conductive line, a resistivity of the second conductive line is lower than a resistivity of the first conductive line, and a resistivity of the high resistance layer is higher than the resistivity of the first conductive line and higher than the resistivity of the second conductive line.Type: GrantFiled: November 17, 2020Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Chul Lee, Whankyun Kim, Joonmyoung Lee, Junho Jeong
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Patent number: 11715817Abstract: Disclosed in an embodiment is a light-emitting element package comprising: a body including a cavity; a light-emitting element arranged on the bottom surface of the cavity and including a first conductive type semiconductor layer, a second conductive type semiconductor layer and an active layer, which is arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a light-transmitting member arranged on the upper part of the cavity, wherein the body includes: a lower body including the bottom surface of the cavity; an upper body including the lateral surface of the cavity; and a first insulating layer arranged between the lower body and the upper body, the lower body includes a first conductive body and a second conductive body insulated and arranged together with the first conductive body, the first conductive type semiconductor layer is electrically connected with the first conductive body, the second conductive type semiconductor layer is electricalType: GrantFiled: March 4, 2019Date of Patent: August 1, 2023Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.Inventor: Koh Eun Lee
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Patent number: 11706999Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.Type: GrantFiled: July 7, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Min Lee, Shy-Jay Lin, Yen-Lin Huang, MingYuan Song, Tung Ying Lee
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Patent number: 11694957Abstract: In a semiconductor device, a device structure is positioned over a substrate, where the device structure includes devices. A wiring structure of the semiconductor device is positioned over the substrate and coupled to at least one of the devices. The wiring structure includes at least one of programmable lines and programmable vertical interconnects, where the programmable lines extend along a top surface of the substrate and the programmable vertical interconnects extend along a vertical direction perpendicular to the top surface of the substrate. The programmable lines and the programmable vertical interconnects include a programmable material having a modifiable resistivity in that the programmable lines and the programmable vertical interconnects change between being conductive and being non-conductive in responsive to a current pattern delivered to the programmable lines and the programmable vertical interconnects.Type: GrantFiled: May 15, 2020Date of Patent: July 4, 2023Assignee: Tokyo Electron LimitedInventors: Mark I. Gardner, H. Jim Fulford, Anton J. deVilliers
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Patent number: 11690299Abstract: Provided is an X-type 3-terminal STT-MRAM (spin orbital torque magnetization reversal component) having a high thermal stability index ? and a low writing current IC in a balanced manner. A magnetoresistance effect element has a configuration of channel layer (1)/barrier layer non adjacent magnetic layer (2b)/barrier layer adjacent magnetic layer (2a)/barrier layer (3).Type: GrantFiled: December 14, 2018Date of Patent: June 27, 2023Assignee: Tohoku UniversityInventors: Hideo Sato, Shinya Ishikawa, Shunsuke Fukami, Hideo Ohno, Tetsuo Endoh
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Patent number: 11682655Abstract: A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.Type: GrantFiled: April 5, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11668766Abstract: A magnetic flux concentrator (MFC) structure comprises a substrate, a first metal layer disposed on or over the substrate, and a second metal layer disposed on or over the first metal layer. Each metal layer comprises (i) a first wire layer comprising first wires conducting electrical signals, and (ii) a first dielectric layer disposed on the first wire layer. A magnetic flux concentrator is disposed at least partially in the first metal layer, in the second metal layer, or in both the first and the second metal layers. The structure can comprise an electronic circuit or a magnetic sensor with sensing plates. The structure can comprise a transformer or an electromagnet with suitable control circuits. The magnetic flux concentrator can comprise a metal stress-reduction layer in the first or second wire layers and a core formed by electroplating the stress-reduction layer.Type: GrantFiled: May 20, 2020Date of Patent: June 6, 2023Assignee: MELEXIS TECHNOLOGIES SAInventor: Appolonius Jacobus Van Der Wiel
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Patent number: 11672186Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.Type: GrantFiled: July 7, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Min Lee, Shy-Jay Lin, Yen-Lin Huang, MingYuan Song, Tung Ying Lee
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Patent number: 11637236Abstract: A spin-orbit torque magnetoresistance effect element according to the present embodiment includes an element part including a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, a spin-orbit torque wiring positioned in a first direction with respect to the element part, facing the first ferromagnetic layer of the element part, and extending in a second direction, a first conductive part and a second conductive part facing the spin-orbit torque wiring at positions sandwiching the element part when viewed from the first direction, and a gate part positioned between the first conductive part and the second conductive part when viewed from the first direction, facing a second surface of the spin-orbit torque wiring on a side opposite to a first surface which faces the element part, and including a gate insulating layer and a gate electrode in order from a position near the spin-orbit torque wiring, inType: GrantFiled: February 1, 2019Date of Patent: April 25, 2023Assignee: TDK CORPORATIONInventors: Tomoyuki Sasaki, Atsushi Tsumita, Yohei Shiokawa
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Patent number: 11637234Abstract: A magnetoresistive memory cell includes an MTJ element including a magnetization free layer and a pure spin injection source. The pure spin injection source includes a BiSb layer coupled to the magnetization free layer. By flowing an in-plane current through the BiSb layer, this arrangement is capable of providing magnetization reversal of the magnetization free layer.Type: GrantFiled: September 14, 2018Date of Patent: April 25, 2023Assignee: TOKYO INSTITUTE OF TECHNOLOGYInventors: Nam Hai Pham, Huynh Duy Khang Nguyen
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Patent number: 11637271Abstract: A method of forming microelectronic systems on a flexible substrate includes depositing a plurality of layers on one side of the flexible substrate. Each of the plurality of layers is deposited from one of a plurality of sources. A vertical projection of a perimeter of each one of the plurality of sources does not intersect the flexible substrate. The flexible substrate is in motion during the depositing the plurality of layers via a roll to roll feed and retrieval system.Type: GrantFiled: October 30, 2020Date of Patent: April 25, 2023Assignee: Universal Display CorporationInventors: Ruiqing Ma, Jeffrey Silvernail, Prashant Mandlik, Julia J. Brown, John Felts
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Patent number: 11631788Abstract: A light-emitting diode structure for improving bonding yield is provided, which includes a light-emitting diode, a plurality of contact electrodes, an insulating layer structure, and a plurality of bonding electrodes. One surface of the light-emitting diode includes a mesa structure. The contact electrodes are on the mesa structure. The bonding electrodes are on the insulating layer structure and respectively cover at least one contact electrode. A surface of one of the bonding electrodes facing away from the light-emitting diode has a first platform and a second platform. The second platform is on the first platform. A surface area of a vertical projection of the second platform on the light-emitting diode is smaller than that of the first platform on the light-emitting diode, and said vertical projection of the second platform is within that of the first platform.Type: GrantFiled: November 30, 2020Date of Patent: April 18, 2023Assignee: Lextar Electronics CorporationInventor: Shiou-Yi Kuo
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Patent number: 11626391Abstract: A light emitting device including a first LED stack, a second LED stack disposed under the first LED stack, a third LED stack disposed under the second LED stack, and a plurality of pillars disposed adjacent to side surfaces of the first, second, and third LED stacks, the pillars including a first pillar commonly electrically connected to the first, second, and third LED stacks, and a second pillar, a third pillar, and a fourth pillar electrically connected to the first, second, and third LED stacks, respectively.Type: GrantFiled: January 15, 2021Date of Patent: April 11, 2023Assignee: Seoul Viosys Co., Ltd.Inventor: Jong Hyeon Chae
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Patent number: 11626553Abstract: A light-emitting apparatus including a circuit substrate and a light-emitting device is provided. The circuit substrate includes a first electrode and a second electrode. The light-emitting device is disposed on a first surface of the circuit substrate. The light-emitting device includes a first conductive terminal and a second conductive terminal. The first conductive terminal and the second conductive terminal are embedded between the first electrode and the second electrode. In a first direction, there is a first distance between an inner edge of the first electrode and an inner edge of the second electrode, there is a second distance between an outer edge of the first conductive terminal and an outer edge of the second conductive terminal, and the first distance is greater than or equal to the second distance.Type: GrantFiled: May 17, 2021Date of Patent: April 11, 2023Assignee: Au Optronics CorporationInventors: Chung En Peng, Chung-Chan Liu
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Patent number: 11626392Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.Type: GrantFiled: February 12, 2021Date of Patent: April 11, 2023Assignee: Silicon Genesis CorporationInventors: Theodore E. Fong, Michael I. Current
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Patent number: 11621291Abstract: A display device includes a substrate, a plurality of pixels, a plurality of inorganic light-emitting elements, and a first light-shielding portion. The pixels are arrayed on the substrate. The inorganic light-emitting elements are provided corresponding to the respective pixels and each have a first side surface and a second side surface opposite to the first side surface. The first light-shielding portion is electrically coupled to the cathode of the corresponding inorganic light-emitting element and prevents output of light traveling in a direction intersecting the first side surface of the inorganic light-emitting element.Type: GrantFiled: November 25, 2020Date of Patent: April 4, 2023Assignee: JAPAN DISPLAY INC.Inventors: Masanobu Ikeda, Yasuhiro Kanaya, Tadafumi Ozaki
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Patent number: 11621380Abstract: A flip-chip of light emitting diode includes at least one reflective layer, at least one N-type electrode, at least one P-type electrode, at least one distributed Bragg reflector, and an epitaxial unit. The epitaxial unit includes a substrate, an N-type layer, an active layer, and a P-type layer, wherein the substrate, the N-type layer, the active layer, and the P-type are sequentially stacked. The epitaxial unit has at least one N-type layer exposed portion, which is extended from the outer side surface of the P-type layer to the N-type layer via the active layer. The at least one reflective layer is formed on the P-type layer, wherein the at least one distributed Bragg reflector is integrally bonded to the N-type layer, the active layer, the P-type layer, and the at least one reflective layer. The at least one N-type electrode is electrically connected with the N-type layer and the at least one P-type electrode is electrically connected with the P-type layer.Type: GrantFiled: July 31, 2018Date of Patent: April 4, 2023Assignee: Xiamen Changelight Co., Ltd.Inventors: Xingen Wu, Yingce Liu, Junxian Li, Qilong Wu
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Patent number: 11610938Abstract: A display panel includes a base layer having a display area and a non-display area including a pad area; a plurality of transistors on the base layer; a first protective layer covering the plurality of transistors; a conductive layer on the first protective layer; a second protective layer over the conductive layer; a first electrode and a second electrode on the second protective layer, the first and second electrodes being spaced from each other; a plurality of light emitting elements between the first electrode and the second electrode; a first contact electrode on the first electrode, the first contact electrode being in contact with one end portion of the light emitting element, and a second contact electrode on the second electrode, the second contact electrode being in contact with the other end portion of the at least one light emitting element; and a first pad in the pad area.Type: GrantFiled: September 16, 2020Date of Patent: March 21, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jin Taek Kim, Jin Yeong Kim, Soo Hyun Moon, Sang Ho Park, Seung Min Lee, Jin Woo Lee, Tae Hoon Yang
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Patent number: 11594489Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.Type: GrantFiled: October 30, 2019Date of Patent: February 28, 2023Assignee: Renesas Electronics CorporationInventors: Toshikazu Hanawa, Kazuhide Fukaya, Makoto Koshimizu