Abstract: A pixel structure includes an original light emitting diode die and a repairing light emitting diode die emitting light of a same color, and an extending conductor. The original light emitting diode die includes a first epitaxial layer, and a first electrode and a second electrode disposed at opposite sides of the first epitaxial layer. The repairing light emitting diode die includes a second epitaxial layer, and a third electrode and a fourth electrode disposed at a same side of the second epitaxial layer. The extending conductor includes a first portion, a second portion and a cut-off region. The first portion is electrically connected to the second electrode of the original light emitting diode die. The second portion is electrically connected to the third electrode of the repairing light emitting diode die. The cut-off region is located in the first portion or between the first portion and the second portion.

Abstract: A display device includes a display panel including a display area and a non-display area, a first output pad set, a second output pad set, and a buffer pad set that are disposed in the non-display area, and a path change circuit. In an exemplary embodiment, the path change circuit is configured to change a signal delivery path such that a signal delivered through the first output pad set or the second output pad set is delivered through the buffer pad set, when an enable signal is input.

Abstract: A display device includes a substrate including a display area to display an image and a pad area positioned around the display area; a first pad unit disposed on the pad area, and including a first terminal region having a plurality of first pad terminals arranged in a first direction; and a printed circuit board including a base film and a second pad unit positioned at one side of the base film, the second pad unit being coupled with the first pad unit by electrically connecting with the plurality of first pad terminals.

Abstract: Provided is a semiconductor device that includes a semiconductor substrate, an interconnection layer that is formed on a first face of the semiconductor substrate, at least one of a structural element that is formed to the interconnection layer, or a structural element that is formed in the semiconductor substrate from the first face side of the semiconductor substrate, a semiconductor-through-electrode that is positioned and formed, from a second face side of the semiconductor substrate opposite to the first face, so as to have a predetermined positional relationship with respect to the structural element, and a metallic-diffusion-preventing insulating layer that is formed from the first face side of the semiconductor substrate in a position, and with a shape, surrounding the semiconductor-through-electrode in the semiconductor substrate.

Abstract: A light emitting device includes: a light emitting element comprising: a semiconductor multilayer structure that has an electrode formation surface, a light-emitting surface opposite to the electrode formation surface, and side surfaces between the electrode formation surface and the light-emitting surface, and a pair of electrodes provided on the electrode formation surface; a covering member covering the side surfaces of the light emitting element; and an optical member disposed over the light-emitting surface of the light emitting element and an upper surface of the covering member, the optical member comprising: a light-reflective portion disposed above the light emitting element, and a light-transmissive portion disposed between the light-reflective portion and the covering member and forming a part of an outer side surface of the light emitting device.

Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

Abstract: The present technology relates to a solid-state image capturing apparatus and an electronic device that can acquire a normal image and a narrow band image at the same time. The solid-state image capturing apparatus includes a plurality of substrates laminated in two or more layers, and two or more substrates of the plurality of substrates have pixels that perform photoelectric conversion. At least one substrate of the substrates having the pixels is a visible light sensor that receives visible light, and at least another substrate of the substrates having the pixels is a narrow band light sensor that includes narrow band filters being optical filters permeating light in a narrow wavelength band, and receives narrow band light in the narrow band.

Abstract: A method of manufacturing an organic light emitting diode (OLED) display device includes: providing a substrate including a display area and a non-display area; forming an organic light emitting diode element in the display area; forming a barrier wall around the display area and spaced apart from the organic light emitting diode element; performing a plasma treatment on the substrate on which the organic light emitting diode element is formed; and forming a thin film encapsulation layer for coating the organic light emitting diode element, wherein forming the thin film encapsulation layer includes: forming at least one inorganic layer; and forming at least one organic layer inwardly of the barrier wall.

Abstract: A light receiving element includes a surface recombination prevention layer composed of a first compound semiconductor on which light is incident; a photoelectric conversion layer composed of a second compound semiconductor; and a compound semiconductor layer composed of a third compound semiconductor, the surface recombination prevention layer having a thickness of 30 nm or less. Also, there are provided an image capturing element including the light receiving element, and an image capturing apparatus including the image capturing element.

Abstract: A display device includes a scan line extending in a first direction. A plurality of data lines cross the scan line. A driving voltage line crosses the scan line. An active pattern includes a plurality of channel regions and a plurality of conductive regions. A control line is connected to the plurality of data lines and the driving voltage line. The active pattern includes a shielding part overlapping at least one data line of the plurality of data lines. The control line includes a plurality of main line parts each extending in the first direction, and a detour part connecting two adjacent main line parts of the plurality of main line parts to each other. The detour part extends along a periphery of the active pattern and crosses the at least one data line of the plurality of data lines.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A field-effect transistor includes a substrate; a source electrode, a drain electrode, and a gate electrode that are formed on the substrate; a semiconductor layer by which a channel is formed between the source electrode and the drain electrode when a predetermined voltage is applied to the gate electrode; and a gate insulating layer provided between the gate electrode and the semiconductor layer. The gate insulating layer is formed of an amorphous composite metal oxide insulating film including one or two or more alkaline-earth metal elements and one or two or more elements selected from a group consisting of Ga, Sc, Y, and lanthanoid except Ce.

Abstract: The present disclosure provides a flexible display device and a manufacturing method thereof. The flexible display device includes a base substrate; a pixel defining layer disposed on the base substrate defining a plurality of light emitting regions; and a first electrode layer disposed on a side of the pixel defining layer away from the base substrate and in light-emitting regions. A thin film encapsulation layer covers the first electrode layer and has protrusions protruding toward the pixel defining layer at a plurality of positions.

Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package featuring a flat plate having a raised edge around its perimeter serving as an anti-stiction device, and an associated method of formation. A CMOS IC is provided having a dielectric structure surrounding a plurality of conductive interconnect layers disposed over a CMOS substrate. A MEMS IC is bonded to the dielectric structure such that it forms a cavity with a lowered central portion the dielectric structure, and the MEMS IC includes a movable mass that is arranged within the cavity. The CMOS IC includes an anti-stiction plate disposed under the movable mass. The anti-stiction plate is made of a conductive material and has a raised edge surrounding at least a part of a perimeter of a substantially planar upper surface.

Abstract: A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

Abstract: The semiconductor device includes at least three semiconductor elements disposed directly or indirectly on a planar member and constituting an upper arm and a lower arm which perform ON and OFF action at mutually differential times; an upper-surface voltage applied region of each semiconductor element is configured to be narrower than an area of the aforementioned whole semiconductor element in planar view; and each semiconductor element is disposed so that the shortest distance between the semiconductor elements constituting the upper arm is formed so as to be longer than the shortest distance between the semiconductor element constituting the upper arm and the semiconductor element constituting the lower arm.

Abstract: An OLED display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to transfer a scan signal, a data line and a driving voltage line crossing the scan line and respectively configured to transfer a data voltage and a driving voltage, and a switching transistor electrically connected to the scan line and the data line and including a switching drain electrode configured to output the data voltage. The display also includes a driving transistor including a driving gate electrode, a driving drain electrode, and a driving source electrode electrically connected to the switching drain electrode. The display further includes a storage capacitor including a first storage electrode electrically connected to the driving gate electrode and a second storage electrode formed on the same layer as the driving voltage line.

Abstract: A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a channel fin over a substrate and forming a top spacer region around a top portion of the channel fin, wherein the top spacer region includes a dopant. A dopant drive-in process is applied, wherein the dopant drive-in process is configured to drive the dopant from the top spacer region into the top portion of the channel fin to create a doped top portion of the channel fin and a top junction between the doped top portion of the channel fin and a main body portion of the channel fin.