Abstract: A method supplies a lighting device with electrical energy, wherein the lighting device includes at least two integrated circuits with at least one LED group by a current source associated with this LED group. The method includes generating a supply voltage by a voltage regulator, adjusting a LED group current passing the LED groups by one of the respective current sources , detecting the voltage drops across the current sources, selecting one voltage drop of each integrated circuit as a characteristic voltage drop, generating a control value of the respective integrated circuit, according to the characteristic voltage drop, reducing the control voltage when the control voltage is greater than a control value of the respective integrated circuit, and controlling the output voltage in accordance with the control voltage and/or in accordance with a control bus voltage derived from the control voltage.

Abstract: The present disclosure discloses a wall switch panel and a light fitting. The wall switch panel includes a touch panel, a micro-control module, and a wireless module. The touch panel has a first communication interface; the micro-control module has a second communication interface and a third communication interface, and the micro-control module is electrically connected with the first communication interface through the second communication interface; the wireless module has a fourth communication interface and is electrically connected with the third communication interface through the fourth communication interface.

Abstract: An architecture for high-performance flip-flops having minimal clock-activated transistors is disclosed. The flip-flops operating in a first voltage domain can receive an input signal from a second voltage domain. The flip-flops include a first latch electrically coupled to a second latch. The first latch includes a first output and a second output. The second latch further includes a first and a second keeper pull-up sub-circuit which electrically couples to the first and second output of the first latch. The clock-gating functionality of the first and second keeper pull-up sub-circuits is merged with the first latch to reduce the loading on the clock signal, and thus the operation of the flip-flop is contention-free and fully-static. An embodiment of the second latch includes only one clock-activated transistor for low-power application. Another embodiment includes two clock-activated transistors for high-speed application.

Abstract: Methods and apparatuses for voltage comparators are described. In one example, a circuit for a voltage comparator includes a first transistor, a second transistor for receiving a first input voltage at a second transistor gate terminal, and a third transistor for receiving a second input voltage at a third transistor gate terminal. The second transistor and the third transistor are connected to the first transistor at a first node. A fourth transistor is connected to the second transistor at a second node, and a fifth transistor is connected to the third transistor at a third node. One or more capacitors are connected between the third node and a fourth node, where the fourth node includes the second transistor gate terminal. One or more capacitors are connected between the second node and a fifth node, where the fifth node includes the third transistor gate terminal. In one example operation, the one or more capacitors provide regenerative gain.

Abstract: An output driving circuit includes: a plurality of bias voltage generating circuits configured to generate a plurality of bias voltages; a switching control circuit; and an output voltage generating circuit. The switching control circuit is configured to selectively connect one bias voltage generating circuit of the plurality of bias voltage generating circuits to the output voltage generating circuit based on an output voltage. The output voltage generating circuit is configured to transmit and receive a parasitic current generated due to transition of the output voltage to and from the one bias voltage generating circuit selectively connected to the output voltage generating circuit through the switching control circuit.

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.

Abstract: A method of duty cycle adjustment includes conditionally inverting an input clock into a conditionally inverted clock; and adjusting a duty cycle of the conditionally inverted clock in one direction in accordance with an integer that represents an amount of duty cycle adjustment, using an uneven clock buffer and a plurality of uneven clock multiplexers that are cascaded and incrementally activated as a value of the integer increments.

Abstract: Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement an RRM that saves both area and power for a given design and is able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to a 50% duty cycle clock.

Abstract: Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.

Abstract: A power supply device is provided. The power supply device includes a power converter and a controller. The controller controls the power converter to generate an output power. The controller includes a first detection circuit and a second detection circuit. The first detection circuit detects the output power to obtain a first detection result. The first detection result is a variation of an output current value of the output power. The second detection circuit detects electrical characteristics other than the output current value to obtain a second detection result. The controller determines whether to limit output of the output power according to a relationship between the first detection result and the second detection result.

Abstract: A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.

Abstract: A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.

Abstract: A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.

Abstract: An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

Abstract: A virtual and parallel power extraction method by using time division, comprising an alternating current load (1), a load end time-division power extraction control device (2), a switch end time-division power extraction control device (3), and a switch end power supply load (4). The alternating current load (1) is connected in parallel with the load end time-division power extraction control device (2); the switch end time-division power extraction control device (3) is connected in parallel with the switch end power supply load (4); a combination body formed by connecting the alternating current load (1) with the load end time-division power extraction control device (2) in parallel and the combination body formed by connecting the switch end time-division power extraction control device (3) with the switch end power supply load (4) in parallel are together connected in series in an alternating current circuit.

Abstract: In an embodiment a device includes a first arrester unit with at least one first gas-filled surge arrester and a second arrester unit with at least one second gas-filled surge arrester, wherein the first and second arrester units are connected in series with one another between a first potential node and a reference potential node, wherein the first arrester unit and the second arrester unit are different from each other, wherein the first arrester unit includes a larger response voltage than the second arrester unit, and wherein the first arrester unit includes a smaller arc voltage than the second arrester unit.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a mixer circuit including a digital-analog converter circuit, a control circuit for controlling the digital-analog converter circuit, a power source control switch, and a plurality of Gilbert circuits. The plurality of Gilbert circuits each include an analog potential holding circuit for holding an analog potential output from the digital-analog converter circuit. The control circuit has a function of outputting a signal for controlling the analog potential holding circuit and the digital-analog converter circuit. The power source control switch has a function of stopping supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated. The analog potential holding circuit includes a first transistor. The first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.

Abstract: A system and methods are provided for group lighting interaction. A lighting infrastructure includes a plurality of simultaneously and independently controllable lighting devices. As various users request access to control the lighting infrastructure, the system and methods involve dynamically partitioning the lighting devices into subsets and then allocating each subset to a corresponding requesting user. The dynamic partitioning may be based on each user's respective location or the time each user requested access to control the lighting infrastructure.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.