Abstract: An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

Abstract: In an embodiment a device includes a first arrester unit with at least one first gas-filled surge arrester and a second arrester unit with at least one second gas-filled surge arrester, wherein the first and second arrester units are connected in series with one another between a first potential node and a reference potential node, wherein the first arrester unit and the second arrester unit are different from each other, wherein the first arrester unit includes a larger response voltage than the second arrester unit, and wherein the first arrester unit includes a smaller arc voltage than the second arrester unit.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a mixer circuit including a digital-analog converter circuit, a control circuit for controlling the digital-analog converter circuit, a power source control switch, and a plurality of Gilbert circuits. The plurality of Gilbert circuits each include an analog potential holding circuit for holding an analog potential output from the digital-analog converter circuit. The control circuit has a function of outputting a signal for controlling the analog potential holding circuit and the digital-analog converter circuit. The power source control switch has a function of stopping supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated. The analog potential holding circuit includes a first transistor. The first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.

Abstract: A system and methods are provided for group lighting interaction. A lighting infrastructure includes a plurality of simultaneously and independently controllable lighting devices. As various users request access to control the lighting infrastructure, the system and methods involve dynamically partitioning the lighting devices into subsets and then allocating each subset to a corresponding requesting user. The dynamic partitioning may be based on each user's respective location or the time each user requested access to control the lighting infrastructure.

Abstract: A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

Abstract: An entropy source circuit is provided. The entropy source circuit includes a digital circuit, a determination circuit and a time-to-digital converter (TDC), wherein the determination circuit is coupled to the digital circuit, and the TDC is coupled to the determination circuit. The digital circuit is configured to generate result data at a second time point according to input data received at a first time point, and the determination circuit is configured to perform determination on reference data with dynamic output generated by the digital circuit, to generate a determination result, wherein the reference data is equal to the result data. In addition, the TDC is configured to perform a time-to-digital conversion on a delay of the digital circuit for generating the result data according to the input data with aid of the determination signal, in order to generate entropy data corresponding to the delay.

Abstract: A control circuit for controlling a data input/output is provided. The control circuit comprises a plurality of control level circuits that include a first control level circuit and a last control level circuit. Each control level circuit has a control element, with a number of control elements of the last control level circuit being greater than a number of control elements of the first control level circuit. Each control element is configured to receive a first control signal and a second control signal, and controls a current for the data input/output depending on the first and second control signals. The control circuit is configured to provide the first control signal to the control elements in a sequence starting at the first control level circuit and ending at the last control level circuit, and then to provide the second control signal to the last control level circuit in reverse order.

Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ?Vbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ?Vbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.

Abstract: A system comprises time-tracking circuitry and phase parameter generation circuitry. The time-tracking circuitry is operable to generate a time-tracking value corresponding to time elapsed since a reference time. The phase parameter generation circuitry operable to: receive the time-tracking value; receive a control signal that conveys a frequency parameter corresponding to a desired frequency of an oscillating signal; and generate a plurality of phase parameters used for generation of an oscillating signal, wherein the generation of the plurality of phase parameters is based on the time-tracking value and the frequency parameter such that the oscillating signal maintains phase continuity across changes in the frequency parameter.

Abstract: A method of controlling current through a transistor is provided. A voltage and current through the transistor are measured. A safe operating current for the voltage is determined. For each of a first sequence of current pulses, a voltage of a voltage pulse applied to a control node of the transistor using a feedback controller is adjusted until the current measured through the transistor is not greater than a first function of the safe operating current. For each of a second sequence of current pulses after the first sequence of current pulses, the voltage of the voltage pulse applied to the control node of the transistor using the feedback controller is adjusted until the current measured through the transistor is not greater than a second function of the safe operating current.

Abstract: An equalizer circuit includes: a main stage circuit including: a main stage differential pair; and a main stage degeneration resistance; a replica stage circuit including: a replica stage differential pair matching the main stage differential pair; and a replica stage degeneration resistance matching the main stage degeneration resistance and disconnected from the replica stage differential pair; equalizer inputs connected to: gate electrodes of the main stage differential pair; and gate electrodes of the replica stage differential pair; and equalizer outputs connected to: a main stage positive output and a main stage negative output connected to drain electrodes of the main stage differential pair; and a replica stage positive output and a replica stage negative output connected to drain electrodes of the replica stage differential pair, the replica stage positive output connected to the main stage negative output and the replica stage negative output connected to the main stage positive output.

Abstract: Programmable clamping methods and devices providing adjustable clamping powers to accommodate different applications and requirements are disclosed. The described devices can use switchable clamping circuits having different structures, body-controlled clamping circuits, or clamping circuits adjusting their input power levels using programmable resistive ladders. Examples of how the disclosed devices can be combined to improve design flexibility are also provided.

Abstract: A post-driver with low voltage operation and electrostatic discharge protection. In one embodiment, a post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver, the output node configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration, the operational amplifier further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit, wherein the current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

Abstract: Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Abstract: A control system for independent alternating-input (“IAI”) devices includes multiple IAI devices and an analog switch component. The control system may also include a bus-generating component. The analog switch component includes multiple switches configured to connect of disconnect input connection points of the analog switch component and voltage input points of the IAI devices. The analog switch component opens or closes switches, responsive to a digital control signal, to provide voltage signals to the voltage input points of the IAI devices. In some cases, the IAI devices activate or deactivate based on the provided voltage signals. In some cases, the bus-generating component provides a first voltage signal to a first voltage input point of an IAI device, and the analog switch component controls the switches to provide a second voltage signal to a second voltage input point of the IAI device.

Abstract: A current stimulator includes a first current generation circuit configured to generate a first current, injectable into a cranial nerve cell, through a current mirroring based on a plurality of transistor pairs; and a second current generation circuit, driven by a clock, configured to generate a second current smaller than the first current by controlling a charge rate based on a voltage difference between terminals of a capacitor. A first output impedance of the first current generation circuit and a second output impedance of the second current generation circuit have a magnitude greater than or equal to a predetermined ratio to a load impedance corresponding to the cranial nerve cell.

Abstract: A level shift circuit includes: a first transistor connected to ground and having a control terminal; a second transistor connected to the ground and having a control terminal connected to the a terminal of the first transistor; a pull-up circuit connected to a power source and also connected to the first terminal of the first transistor, and having a current mirror circuit constituted by two transistors; a third transistor having a first terminal connected to the first terminal of the first transistor, a second terminal connected to the power source, and a control terminal connected to a first terminal of the second transistor; and a fourth transistor having a first terminal connected to the first terminal of the second transistor, a second terminal connected to the power source, and a control terminal connected to the first terminal of the first transistor.

Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.

Abstract: An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.

Abstract: Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.