Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.

Abstract: An apparatus includes a capacitor coupled to a power switch, wherein the capacitor is configured to provide a negative gate voltage to the power switch when a turn-off signal is applied to a gate of the power switch, and a sink and source power supply coupled to the capacitor, wherein the sink and source power supply has a first current limit for controlling a sink current flowing from the capacitor to the sink and source power supply, and a second current limit for controlling a source current flowing from the sink and source power supply to the capacitor.

Abstract: One embodiment is a reconfigurable mixer topology for selectively implementing one of a harmonic rejection mixer (HRM) and a subharmonic mixer (SHM), the reconfigurable mixer topology comprising a mixer core comprising a plurality of differential mixers each having a first clock input and a second clock input; a clock generator for generating a plurality of clock signals each having a different phase; and a clock distributor for distributing the plurality of clock signals to the first and second clock inputs of the differential mixers in accordance with a designated operation of the reconfigurable mixer as an HRM or an SHM.

Abstract: The present disclosure relates to a latch circuit and a latch method, and an electronic device, and relates to the technical field of integrated circuits. The latch circuit includes: a transmission module, a latch module, and a control module, wherein the transmission module is configured to transmit an input signal to the latch module; the latch module is configured to latch the input signal or output the input signal when a set signal or a reset signal is at a low level; and the control module is configured to perform control, such that a current leakage path cannot be formed between the transmission module and the latch module when the set signal or the reset signal is at a high level.

Abstract: A clock filter device for finding an optimal cut-off frequency of a clock filter through a controller to achieve an effective clock filtering is illustrated. Further, in the calibration mode, a reference clock that has not passed the clock filter and a reference clock that has passed the clock filter make a first counter and a second counter count respectively. After the first counter counts to a specific value, a count value of the second counter is obtained. The count values of the first counter and the second counter are compared to each other to determine whether the two values are approximate or not. When the two values are not approximate, the previous cut-off frequency of the clock filter is taken as the optimal cut-off frequency. Therefore, the clock filter can adopt the optimal cut-off frequency in a working mode to effectively filter out the noise an input clock.

Abstract: A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.

Abstract: A clock generation circuit, a latch using same, and a computing device are provided. The clock generation circuit includes an input end, configured to input a pulse signal; a first output end, configured to output a first clock signal; a second output end, configured to output a second clock signal; and an input drive circuit, a latch circuit, an edge shaping circuit, a feedback delay circuit, and an output drive circuit, where the input drive circuit, the latch circuit, the edge shaping circuit, the feedback delay circuit, and the output drive circuit are sequentially connected between the input end and the first output end as well as the second output end in series. A clock pulse can be effectively shaped, the use of a clock buffer can be reduced, and the correctness and accuracy of data transmission and latching can be improved.

Abstract: Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.

Abstract: A counting circuit and a chip are disclosed. The counting circuit includes a charge counter module including a pulse processing module and a first capacitor. The pulse processing module is configured to covert a received pulse signal into a counting current and to transfer the converted counting current to the first capacitor. The first capacitor is configured to receive the counting current and store charge carried in the counting current. The counting circuit takes a voltage of the first capacitor as a basis for counting.

Abstract: An apparatus is disclosed for mixing signals. In example aspects, the apparatus includes a mixer circuit having multiple local oscillator nodes, a first node corresponding to a first frequency, and multiple second nodes corresponding to a second frequency. The mixer circuit includes multiple capacitors coupled between the multiple local oscillator nodes and the multiple second nodes. The mixer circuit has multiple switches including a first switch, a second switch, a third switch, and a fourth switch. The multiple switches are coupled between the multiple capacitors and the multiple second nodes. The first switch and the second switch are coupled between the multiple capacitors and the first node. The first switch and the second switch are disposed between the fourth switch and the third switch.

Abstract: Embodiments of the present disclosure provide a driving circuit and a lamp comprising the same. The driving circuit comprises inputs connected to a mains supply; outputs connected to an LED load; an output capacitor connected in parallel with the LED load; an LED driving current source connected to the outputs, and configured to convert the mains supply at the inputs to current at the outputs in an illumination mode, such that the current flows through the LED load and charges the output capacitor; and a control circuit configured to receive a standby signal to enable a standby mode, and to control the mains supply to linearly charge the output capacitor in the standby mode, such that an output voltage at the output can be lower than a turn-on voltage of the LED load and is higher than a preset lowest voltage.

Abstract: A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is different from the data input circuit.

Abstract: A method and apparatus for input matching of a passive mixer are disclosed. The passive mixer includes a differential transistor pair including a first transistor and a second transistor, a first inductor having one end connected to the first transistor and another end connected to a ground, a second inductor having one end connected to the second transistor and another end connected to a ground, and a third inductor having one end for receiving a radio frequency (RF) signal and another end connected to a ground.

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) includes first and second semiconductor switches, a transformer, a capacitor, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducted through a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The capacitor is electrically coupled between the junction of the first and second semiconductor switches and the primary winding. The current sense circuit receives a sense voltage and averages the sense voltage when the first semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

Abstract: The present invention provides a system comprising PoE apparatus including midspans, switches and routers that can provide high powered PoE connections that enable the recovery of DC power in sufficient quantities that allow it to be converted to AC power by way of an inverter. The invention also provides a method for providing AC power, data and light to office workstations using a single PoE connection. The invention further comprises a common mode signalling system that operates independently of any TCP/IP signal transmitted through an Ethernet connection wherein said signalling system is adapted to communicate with and control PoE powered devices.

Abstract: An overcurrent detector with an electric line and a sensor for monitoring an electric current in the line and outputting a measurement signal, and an integral-unit adapted to integrate an interval of consecutive values of the measurement signal and outputting an integrator-signal, the detector comprises a comparator unit for comparing a value of the integrator-signal with a threshold level and outputting a trigger signal, with the detector further comprises a threshold level determination unit, an input being connected to the sensor for receiving an actual measurement signal, and with an output being connected to the comparator unit, proving the comparator unit with the threshold level, and that the threshold level determination unit is adapted to determine the threshold level in dependence on the value of the actual measurement signal.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: A travelling wave mixer (TWM) is provided that includes an input artificial transmission line configured to transmit an input signal, an output artificial transmission line configured to transmit an output signal, a local oscillator (LO) artificial transmission line configured to transmit an LO signal, and a plurality of mixer stages connected in parallel between the output artificial transmission and the input artificial transmission line. Each of the mixer stages includes an input amplifier, a mixer and an output amplifier connected in series between the input artificial transmission line and the output artificial transmission line, where an input of the mixer receives an output of the input amplifier, and an output of the mixer is applied to an input of the output amplifier.