Abstract: One embodiment comprises a substrate having a top surface for receiving a semiconductor die. According to a disclosed embodiment, an inductor is patterned on the top surface of the substrate. The inductor is easily accessible by connecting its first and second terminals to, respectively, a substrate signal bond pad and a semiconductor die signal bond pad. In another disclosed embodiment, an inductor is fabricated within the substrate. The inductor comprises via metal segments connecting interconnect metal segments on the top and bottom surfaces of the substrate. The first and second terminals of the inductor are easily accessible through first and second substrate signal bond pads. One embodiment comprises at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and a printed circuit board attached to the bottom surface of the substrate.

Abstract: A semiconductor device and a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for electrically connecting to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions. Accordingly, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.

Abstract: A method of manufacturing a semiconductor device comprising a step of forming a plurality of resin layers, an interconnect connected electrically to an electrode of each of a plurality of semiconductor elements, and an external terminal connected electrically to the interconnect, on an aggregate of semiconductor elements having an electrode, and a step of cutting the aggregate, wherein at least one resin layer among the plurality of resin layers is formed avoiding a cutting region of the aggregate.

Abstract: A semiconductor chip package is disclosed. The package includes a substrate, a metallization layer formed on one side of the substrate and a semiconductor die mounted on the substrate. The semiconductor die is electrically connected to a portion of the metallization layer. A shield element is mounted on the substrate and electrically connected to a portion of the metallization layer.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.

Abstract: An optical integrated circuit application where the integrated circuit is packaged in a clear molding material and is attached to a printed circuit board having an aperture is described. The integrated circuit senses and/or emits light through the clear molding material and through the aperture in the printed circuit board.

Abstract: A method of making a compliant microelectronic package includes providing a first substrate having a top surface with conductive pads and an opening extending therethrough to the first substrate so that a bottom surface of the second substrate confronts a top surface of the first substrate. A microelectronic element is attached to the first substrate so that a back face of the microelectronic element confronts the top surface of the first substrate. The contacts of the microelectronic element are electrically interconnected with the conductive pads of the second substrate. A dielectric sheet having conductive leads is juxtaposed with the first substrate. The second ends of the leads are electrically interconnected with the conductive pads of the second substrate, and the dielectric sheet and the second substrate are moved away from one another so as to vertically extend the leads.

Abstract: A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.

Abstract: A semiconductor device comprising integrated circuit elements realized by means of a stack of layers of semiconductor materials provided on a substrate of semiconductor material and comprising means for preventing the pollution of the circuit elements and of the substrate by hydrogen originating from their environment is characterized in that said means are formed by a layer of a material which absorbs hydrogen (or hydrogen getter) (10), which forms a pattern which is integrated with the circuit elements and whose outer surface (11) is exposed and in contact with the environment. This device, of the MMIC type, forms part of a module of a spatial or terrestrial telecommunication system.

Abstract: A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.

Abstract: Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical dehydroxylation operation, wherein the halogen compound may be NH4F or CCl4.

Abstract: A chip with beveled edges suitable for adhering onto a surface of a die pad by an adhesive material. The chip has an active surface and a corresponding back surface, wherein the active surface has beveled edges. The back surface of the chip is adhered onto the surface of the die pad by the adhesive material.

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Abstract: In one embodiment, the invention includes first and second transmission lines fabricated in a redistribution layer over a semiconductor die. The first transmission line has a first distance from a first ground return path formed in a first metal level. The first transmission line has a first impedance corresponding to the first distance. In other words, the impedance of the first transmission line is affected by the distance between the first transmission line and the first ground return path. Similar to the first transmission line, the second transmission line has a second distance from a second ground return path formed in a second metal level. The second transmission line has a second impedance corresponding to the second distance. In other words, the impedance of the second transmission line is affected by the distance between the second transmission line and the second ground return path.

Abstract: A lead frame includes a die pad, a suspension lead and a plurality of leads. The group of leads include at least three kinds of leads, including first, second and third leads. While the first lead and the third lead are connected to each other upon production of the lead frame, a connecting portion therebetween has a smaller thickness than that of the frame body so that the first lead and the third lead can be separated from each other in a subsequent step.

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die having a vertical power transistor, a first surface and a second surface. A ground plane proximate the second surface and distal to the first surface. A bus member covers a portion the first surface of the semiconductor die and has at least one leg that electrically couples a source region of the semiconductor die to the ground plane.

Abstract: A microelectronic device is provided including an integrated circuit mounted to a substrate. A break through multiple conductive layers of the substrate corresponds to a break in the power planes of the integrated circuit. The breaks in the substrate and in the integrated circuit allow for a rotational burn-in of a first portion and a second portion of the integrated circuit.

Abstract: An integrated circuit chip including a circuit board unit and a plurality of contact pads on a top surface of the unit. A die having a plurality of solder pads is positioned adjacent the circuit board unit with the solder pads wire-bonded to the contact pads. A lead frame having connecting leads is positioned on the circuit board unit with the leads connected to the solder pads via a conductive contact layer. A plastic layer encapsulates the circuit board unit and at least a portion with the lead frame.