Abstract: The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.

Abstract: A transfer mark structure for a multi-layer interconnecting process for avoiding the influence of dishing when a groove pattern for multi-layer interconnection is formed, and for improving the accuracy and stability of reading the transfer mark used for transfer in the following step so as to align with a location of transfer in the preceding step, and a method for producing such a transfer mark for the multi-layer interconnecting process. The underlying layer 102 immediately under the transfer mark 22 for photoengraving formed in the step of connecting between interconnecting layers 16 has a groove-like pattern.

Abstract: A concentrically leaded power semiconductor package includes two or more generally concentric conductors. An inner conductor may provide an attachment point for one or more semiconductor devices at an end of the inner conductor and an electrical connection at an opposite end. An outer conductor may be pressed onto the inner conductor and may be separated by an electrical insulator. A semiconductor device, such as a light emitting diode (LED), may be attached to the inner conductor by epoxy gluing or by soldering, and may be attached to the outer conductor by a bonding wire. The package may be cylindrical or a rectangular solid. The package may incorporate additional semiconductor mounting surfaces and more than two conductors.

Abstract: The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.

Abstract: A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.

Abstract: A method and apparatus for testing unpackaged semiconductor dice having raised contact locations are disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

Abstract: A power module substrate includes a ceramic substrate having a circuit pattern formed thereon, and a metal frame with which the ceramic substrate can be joined to a water-cooling type heat sink. The metal frame has a thickness equal to that of the ceramic substrate or the ceramic substrate having the circuit pattern, and is provided with plural perforations formed therein. Metal thin sheets having through-holes in communication with the corresponding perforations, and containing contacting portions having the undersides thereof contacted to at least a part of the circumferential surface of the ceramic substrate are disposed on the surface of the metal frame. In a semiconductor device, a semiconductor element is mounted onto the circuit pattern, and the power module substrate is joined directly to the water-cooling type heat sink by inserting male screws through the through-holes and the perforations, and screwing the male screws in the female screws of the water-cooling type heat sink.

Abstract: A semiconductor device having improved metal line structure has a first dielectric layer formed on a semiconductor substrate, a metal film pattern formed on the first dielectric layer, an interface protection layer on the metal film pattern, and a second dielectric layer on the interface protection layer, wherein the second dielectric layer contains a reactive material, e.g., fluorine, which is prevented by the interface protection layer from diffusing to the metal film pattern and reacting with the metal in the metal film pattern to form a damage film, e.g., metal fluoride, which is a highly resistive material that, if formed on the semiconductor device, would reduce the reliability of the metal film pattern and thus reduce the reliability of the semiconductor device as a whole.

Abstract: A heat dissipating element (e.g., a heat sink) is held in an initial position closer to a heat generating structure (e.g., a microprocessor) and in a subsequent position farther from the microprocessor. A thermal interface material (e.g., a thermal grease) spans the gap, but is not held under compression, between the heat sink and the microprocessor.

Abstract: A method is for forming an intermediate dielectric layer to optimize the planarity of electronic devices integrated on a semiconductor which incorporate non-volatile memories. The insulating dielectric is deposited from a liquid state source comprising silicon oxides and organics of the resist type. The liquid dielectric layer is evenly spread by a spinning technique providing good levels of planarity. Solidification, referred to as polymerization, is achieved through a low-temperature thermal cycle. Since this dielectric layer cannot be used as such to isolate the semiconductor substrate from the overlying metallization plane on account of the presence of organics forming a source of impurities, it is arranged for the layer to be encapsulated between two dielectric layers of silicon oxide as deposited from a plasma.

Abstract: In a semiconductor device of the present invention and a production method thereof, an electronic circuit is provided in a semiconductor substrate, the electronic circuit having terminals. An internal wiring pattern is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals. A protective layer is provided on the substrate, the protective layer covering the substrate. Vias are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate. An external wiring pattern is provided on the protective layer, the external wiring pattern being connected to the vias. Projection electrodes are connected to the external wiring pattern, the projection electrodes having a predetermined height above the external wiring pattern.

Abstract: A lead frame for a semiconductor package and a method for manufacturing the lead frame. In the manufacture of the lead frame, a protective layer is formed with nickel (Ni) or Ni alloy on a metal substrate, an intermediate layer is then formed with palladium (Pd) or Pd alloy on the protective layer. Then, Pd and gold (Au) are alternately plated on the surface of the intermediate layer to form an outermost layer including both Pd and Au particles thereon.

Abstract: In a vertical cavity surface emitting laser (VCSEL), the metal contact area, the associated metal bonding pad and the interconnecting metal bridge are deposited on top of a conductive upper mirror stack. To prevent current flow from the pad through the conductive mirror stack which would bypass the active medium, a moat is etched surrounding the pad area. The moat isolates the pad area and the conductive material beneath the pad area. In a method of making a VCSEL, the semiconductor layered portion of an optical semiconductor device is first formed on a suitable substrate. Such semiconductor layers can include various layers of conductive, semiconductive or insulating material as may be required for the type of device being constructed. The metal contact and the metal bonding pad areas together with an interconnecting metal bridge are then deposited on the surface of the semiconductor layers.

Abstract: A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

Abstract: A semiconductor device including at least one die bond pad; at least one semiconductor element mounted on the at least one die bond pad; a plurality of substantially parallel wire bond pads connected to electrodes of the at least one semiconductor element, and disposed substantially in parallel to the at least one die bond pad in a longitudinal direction; and a sealing resin configured to mold the at least one semiconductor element, wherein back surfaces of the at least one die bond pad and the plurality of parallel wire bond pads are free from the sealing resin.

Abstract: A multi-layered integrated semiconductor device incorporates an upper and lower IC chips which are connected with each other via a first set of wiring pads of the upper IC chip to a second set of wiring pads of the lower IC chip. The device is provided with a multiplicity of pair-wise connected external monitoring terminals on the periphery of the upper IC chip, and a multiplicity of monitoring pads on the lower IC chip, in opposition to the pair-wise connected monitoring pads, so that pad-to-pad resistances between the pads of the upper and lower IC chips can be externally measured by directly connecting the monitoring pads to the external terminals.

Abstract: A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

Abstract: Structures within semiconductor devices having a titanium alloy layer are provided. The titanium alloy layer is formed through chemical vapor deposition by combining a first precursor with a reducing agent to form a seed layer, and by combining a second precursor with the seed layer to form the titanium alloy layer. Structures are described having a titanium alloy layer on sidewalls and an exposed base layer of a contact hole. Structures are further described having a titanium alloy layer on sidewalls of a contact hole and a titanium silicide layer on an exposed base layer of the contact hole. The structures are useful as device contacts to active areas of a semiconductor device, and as interlevel vias within semiconductor integrated circuits.

Abstract: A microcap wafer-level package is provided in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer has gaskets formed thereon using a thick photoresist semiconductor photolithographic process. Bonding pad gaskets match the perimeters of the bonding pads and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer. The cap wafer is then placed over the base wafer to cold weld bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket. The cap wafer is then thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for connecting wires from a micro device utilizing system.

Abstract: A method for fabricating an integrated circuit chip includes the steps of: (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit; (b) forming a die having an upper surface provided with a plurality of solder pads; (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed; (d) wire-bonding the solder pads to the contact pads via conductive wires; (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.