Abstract: A structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.

Abstract: A semiconductor device using TCP structure, includes a first semiconductor chip mounted on a tape carrier by ILB and a second semiconductor chip mounted on the tape carrier by stacking onto the first semiconductor chip. The first semiconductor chip is arranged so that a first electrode, formed on a surface of the first semiconductor chip, is connected to an inner lead via a first gold bump. The second semiconductor chip is arranged so that a third electrode formed on the second semiconductor chip is connected to a second electrode formed on the same surface as the first electrode via a second gold bump. In this fashion, it is possible to reduce a terminal pitch of the semiconductor device on which more than one semiconductor chip are mounted.

Abstract: A multichip module that utilizes an angled interconnect to electrically interconnect chips in the module that are positioned at an angle relative to each other. The multichip module may comprise a first and second chips that are positioned in an orthogonal manner. The first and second chips are electrically interconnected via an interconnect structure comprising a first conductive pillar that extends from an outer surface of the first chip. A distal end of the first pillar is electrically connected to an outer surface of the second chip via a solder ball or another conductive pillar that is interposed between the distal end of the first conductive pillar and the second chip.

Abstract: A high-density memory card comprises a base card and two packages fixedly mounted within the base card. The two packages are attached to the base card and face each other. In one embodiment, a first package comprises a first substrate and at least one memory chip, and a second package comprises a second substrate and at least one memory chip. A first surface of the first substrate has external connection pads formed thereon and is exposed from the memory card. A second surface of the first substrate has first connection pads formed thereon. The memory chips are mounted on the second surface and electrically connected to each other. A third surface of the second substrate is exposed from the memory card, and a fourth surface of the second substrate has second connection pads formed thereon. The memory chips are mounted on the fourth surface and electrically connected to each other.

Abstract: Methods and apparatus for mounting a semiconductor to a heat sink. A clamp is provided comprising a spring beam mounted to a clamp body, wherein the body restricts the spring beam ends and the spring beam has a convex curvature relative to an adjacent power semiconductive module. The portion of the spring beam near its apex contacts the module, applying force to bias a heat-transmitting surface of the module against a heat sink. When temperature increases, the spring beam expands to add additional clamping force to the module. Further embodiments provide making the spring beam from a material having a high coefficient of thermal expansion and the clamp body from a material having a low coefficient of thermal expansion, further increasing the force that may be applied by the spring beam with increases in temperature. The spring beam may comprise layers of different materials to increase the applied force.

Abstract: An adhesion layer made from Al film or Ti film is formed on Cu electrode pad portions as external connection terminals of a Cu interconnection layer of an LSI formed on the surface layer of a semiconductor substrate. A BLM film having a stacked structure of Cr/Cu/Au or Ti/Cu/Au is formed on the adhesion layer. Solder ball bumps made from Pb and Sn are formed on the BLM film. The adhesion layer ensures a high adhesion strength and a high electric contact characteristic between the Cu electrode pad portions and the BLM film, that is, between the Cu electrode pads and the solder ball bumps.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract: An improved method of attaching a semiconductor die to an organic substrate and an improved semiconductor package are herein disclosed. The die package comprises a die secured to a printed circuit board (PCB) with an adhesive tape. The adhesive tape may be of single or multi-layer construction. In one embodiment, a tri-layer tape is disclosed having a carrier layer sandwiched between two identical adhesive layers. In one embodiment, a method is disclosed utilizing a pressure sensitive, thermoset adhesive tape. In another embodiment, a method is disclosed utilizing a B-stageable thermoset adhesive. In yet another embodiment, a method using a pressure sensitive adhesive is disclosed. In still yet another embodiment, a method is disclosed wherein the adhesive is a hybrid material having both thermoset and thermoplastic components.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new “self-trenching” or “self-planarizing” method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer.

Abstract: A composite component of the invention has a structure of laminating a coil composed of at least one layer of conductor layer and at least one layer of insulator layer, and a capacitor composed of at least one layer of electrode layer and at least one layer of dielectric layer. And, it also includes, if necessary, an internal conductor for electrically connecting the coil and capacitor. Further, plural coil elements and capacitor elements are provided in a same layer. According to such constitution of the invention, composite components having various types of filter circuits can be manufactured easily by slight process condition changes. As a result, composite components for noise reduction can be mass produced efficiently, and a high productivity is obtained.

Abstract: A semiconductor part for component mounting, a mounting structure and a mounting method providing ample surplus wiring pitch and width between terminals in order to improve the strength of the connection with the printed circuit board in view of the recent trends towards a greater number of pins and greater component mounting density on printed circuit boards or substrates. A semiconductor component for mounting has area terminals comprised of area terminals mounted on the outer circumferential side and area terminals mounted on the inner circumferential side of the board. The area terminals on the outer circumferential side of the board are arranged with a larger pitch and or diameter than the area terminals on the inner circumferential side.

Abstract: The present invention provides a resin-sealed semiconductor IC package of a large integration size having a size substantially equal to that of its component semiconductor IC chip. The resin-sealed semiconductor IC package comprises a semiconductor IC chip, a plurality of leads arranged on the semiconductor IC chip and having end portions bent so as to extend perpendicularly to the major surface of the semiconductor IC chip, a resin molding sealing the semiconductor IC chip and the leads therein so that the tips of the end portions of the leads are exposed on one surface thereof, and conductive elements connected respectively to the exposed tips of the leads.

Abstract: A semiconductor component includes a chip carrier having a first surface, a second surface, and openings therein. At least one semiconductor chip is mounted on the chip carrier. Soldering connection points are formed by at least one metal foil that lines the openings and that extends through the openings. Contact-making points are connected to the semiconductor chip and form electrically conductive connections which extend through the openings in the chip carrier to the soldering connection points. A further metal foil is located between the semiconductor chip and the chip carrier and forms a soldering connection point. The openings include at least one opening that is located underneath the semiconductor chip. The further metal foil extends through the opening that is located underneath the semiconductor chip to the first surface and to the second surface.

Abstract: A method of making a microelectronic assembly including a compliant interface includes providing a first support structure, such as a flexible dielectric sheet, having a first surface and a porous resilient layer on the first surface of the first support structure, stretching the first support structure and bonding the stretched first support structure to a ring structure. The first surface of a second support structure, such as a semiconductor wafer, is then abutted against the porous layer and, desirably after the abutting step, a first curable liquid is disposed between the first and second support structures and within the porous layer. The first curable liquid may then be at least partially cured.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: A semiconductor device characterized by comprising a first insulating film formed on the semiconductor substrate, a first wiring or mark formed on the first insulating film, an electrically isolated pattern formed under the first insulating film and below the first wiring or mark, a hole formed in the first insulating film to connect the first wiring or mark and the electrically isolated pattern, and a second insulating film for covering the first wiring or mark.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A lead frame comprising a plurality of leads and a die pad disposed at a position surrounded by top ends on one side of the leads, wherein at least the outermost layer on the obverse of the die pad comprises a nickel plated layer, as well as a semiconductor device comprising the lead frame and a semiconductor element mounted by way of a bonding agent on the nickel plated layer at the obverse of the die pad.

Abstract: A circuit board includes a wiring board 2 and plural integrated circuit chips (LSI 1) mounted on the wiring board. At least one of the integrated circuit chips is mounted on a first surface of the wiring board 2 as a flip chip and the part mounted as a flip chip is sealed with resin. Further, a bare plate (a flat plate 5) is mounted on a second surface of the wiring board 2 with a resin (sealing resin 3) opposite the first surface where the integrated circuit chip mounted as a flip chip.