Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and a second sidewall wherein the first sidewall is opposite the second sidewall. The first sidewall has a stair step configuration such that the first sidewall is closer to the second sidewall at the bottom of the opening than at the top of the opening. A conductive film is then formed on the first sidewall in the opening and on the bottom of the opening on the conductive film.

Abstract: Disclosed is a semiconductor package which has no resinous flash formed on a lead frame and its manufacturing method.

Abstract: A structure and method for fabricating integrated circuits with improved electrical performance. The structure comprises electronic devices formed along a semiconductor surface, a first upper level of interconnect members over the semiconductor surface, a lower level of interconnect members formed between the semiconductor surface and the first upper level, and insulative material positioned to electrically isolate portions of the upper level of interconnect members from one another. The insulative material comprises a continuous layer extending from within regions between members of the upper interconnect level to within regions between members of the lower interconnect level and is characterized by a dielectric constant less than 3.9. The method begins with a semiconductor layer having electronic device regions thereon. A first insulative layer is deposited over the electronic device regions and a lower level of interconnect members is formed over the first insulative layer.

Abstract: A transistor (200) is provided with a semiconductor chip (1) inside a resin package (20). An outer lead (41, 42, 43, 44) is arranged on a first side surface (23) of the resin package (20) to serve as an external drain electrode. A lead frame (5) includes the outer lead (41, 42, 43, 44) and a sheet-like portion (51). The sheet-like portion (51) is connected to a first surface (1a) of the semiconductor chip (1) for holding a drain electrode. An outer lead (45, 46, 47, 48) is arranged on a second side surface (24) of the resin package (20) to serve as an external source electrode. The outer lead (45, 46, 47, 48) is connected by a wire (4) to a second surface (1b) of the semiconductor chip (1) for holding a source electrode. An ejector pin site (22) formed on a top surface (21) of the resin package (20) is located on the side of the first side surface (23).

Abstract: An alignment mark (51) is formed on the surface (64) of a silicon carbide substrate (50). The alignment mark (51) is used to reflect a light signal (72) to determine the proper position for the silicon carbide substrate (50). The materials that are used to form the alignment mark (51) can be used to form an alignment mark on any transparent or semi-transparent substrate and will maintain physical integrity through very high temperature processing steps.

Abstract: A semiconductor interconnection device having a semiconductor die, a plurality of epoxy bonds, and an array of insulating islands is disclosed. The semiconductor die has a plurality of conductive contacts. The plurality of epoxy bonds has a metallic substance such as silver. The epoxy bonds are configured to provide interconnection between the semiconductor die and an external structure. The plurality of epoxy bonds is selectively applied to the plurality of conductive contacts on the semiconductor die and corresponding conductive contacts on the external structure. The array of insulating islands is coupled to the plurality of conductive contacts. The islands are configured to prevent migration of the metallic substance from the plurality of epoxy bonds to the semiconductor die through the plurality of conductive contacts.

Abstract: A semiconductor package and a method for fabricating a semiconductor package are disclosed. In one embodiment, the semiconductor package includes an exposed portion of a conductive strap at a package horizontal first surface and exposed surfaces of multiple leads at a package horizontal second surface. A power semiconductor die is mounted on a die pad connected to at least one lead having an exposed surface. Heat generated by the die within the package may be dissipated through thermal paths including the exposed surfaces.

Abstract: To provide a semiconductor device that is capable of transmitting heat evolved in an active element efficiently to a heat sink member, and a manufacturing method for the semiconductor device. One of the terminals (such as drain electrode) of an active element formed in a substrate of, for example, GaAs, is thermally contacted with a heat sink member via an insulating member of, for example, aluminum nitride, exhibiting thermally conductive and electrically insulating properties. The heat sink member may, for example, be an electrically conductive member connected to another terminal of the active element, or a heat sink of a package.

Abstract: A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage number of each chip are formed and the fuses are selectively cut off so as to permit each chip to individually receive a chip control signal.

Abstract: A semiconductor device has a first semiconductor chip and a second semiconductor chip superposed on and bonded to the surface of the first semiconductor chip. In the region on the first semiconductor chip where the second semiconductor chip is bonded thereto, connection pads are arranged in positions that fit a plurality of predetermined types of semiconductor chips. On the second semiconductor chip, connection pads are arranged in positions that fit the connection pads arranged on the first semiconductor chip.

Abstract: A semiconductor device in a computer system is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond.

Abstract: Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size. A lower die has keep out areas on its top surface. The keep out areas correspond to two adjacent edges of the lower die. The lower die has bond pads within the keep out areas. An upper die is stacked on the top surface of the lower die such that the bond pads within the keep out areas of the lower die are exposed to accept wire bonds. The configuration of the keep out areas next to adjacent edges of the lower die thus provides flexibility in the design of stacked chip packages because the size of the upper die is not limited by the bond pad configuration of the lower die.

Abstract: A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in an encapsulation material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.

Abstract: A semiconductor device includes a semiconductor substrate which has a first main surface having circuit elements formed thereon, a second main surface substantially opposite to the first main surface, and a plurality of side faces provided between the first main surface and the second main surface. The semiconductor device also includes a plurality of external terminals formed over the first main surface and respectively electrically connected to the circuit elements. The second main surface has a central area and a peripheral area surrounding the central area, and a first steplike section formed in the peripheral area.

Abstract: The present invention is to provide a chip type electronic part without the risk of generating a tombstone at the time of soldering on a circuit substrate. External electrodes are formed at both end parts of an electronic part element, with the external electrodes comprising electrodes at the base layer formed as a thin film and solders at the outermost layer, with the solders at the outermost layer containing Sn and Pb as the main component and 0.1 to 0.4% by weight of Ag.

Abstract: A thermal management system for a semiconductor chip including at least one region of thermally conductive material included internally within the semiconductor chip.

Abstract: A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin deposited on the upper surface of the semiconductor chip, encapsulating the terminals but exposing at least some of them to a predetermined height; and electroconductor members such as solder balls connected to the terminals. There is also disclosed a method of fabricating such a semiconductor device.

Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

Abstract: The present invention discloses a method of manufacturing a dual chip package using tape wiring boards. According to the method, an upper tape wiring board, a lower tape wiring board, and a lead frame are prepared. Each of the tape wiring boards includes a polymeric tape having windows patterned therein, metal patterns formed on the lower surface of the polymeric tape at either sides of said windows. The metal patterns have pad connection portions exposed through the window. Lead connection portions extend outwardly from said polymeric tape. An adhesive layer is formed on the lower surface of the tape. A lower chip is attached to a lower surface of the die pad. The lower chip includes an active surface having a plurality of electrode pads at approximately the center and a rear surface attached to the lower surface of the die pad. An upper chip is attached to an upper surface of the die pad.