Abstract: A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor.

Abstract: The present invention relates to an organic light-emitting diode, an array substrate and a preparation method thereof, and a display device. The organic light-emitting diode comprises an anode, a cathode, a light-emitting layer disposed between the anode and the cathode, and a hole injection layer disposed between the anode and the light-emitting layer, wherein the hole injection layer is provided therein with metal nanoparticles, and the frequency of a localized surface plasmon resonance of the metal nanoparticles is matched with the emission wavelength of the light-emitting layer. As the organic light-emitting diode is doped with metal nanoparticles in the hole injection layer and the resonance frequency of the localized surface plasmon of the metal nanoparticles is matched with the emission wavelength of the light-emitting layer, the metal nanoparticles are allowed to generate localized plasma resonance with photons, so that the light extraction efficiency of the organic light-emitting diode is enhanced.

Abstract: A MEMS device comprises a first layer (1), a second layer (2) and a third layer (3) sealed together. A mobile structure (7.1, 7.2) in the second layer (2) is defined by openings (8.1, 8.2) in the second layer (2). In the first layer (1), there is at least one first-layer cavity (6.1, 6.2) with an opening towards the mobile structure (7.1, 7.2) of the second layer (2). In the third layer (3), there is at least one third-layer cavity (9) with an opening towards the mobile structure (7.1, 7.2) of the second layer (2). Therefore, the third-layer cavity (9) and the second layer (2) define a space within the MEMS device, A getter layer (10.1, 10.2) arranged on a surface of said space. The getter layer (10.1, 10.2) is preferably arranged on a surface of the second layer (2) and in particular, the getter layer (10.1, 10.2) is arranged on a static part of the second layer (2). Alternatively, the MEMS device has a third-layer cavity (24) with at least two recesses (25.1, 25.2, 25.3) and the getter layer (26.1, 26.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; forming a barrier layer in the trench; forming a conductive layer on the barrier layer; performing a first etching process to remove part of the conductive layer; and performing a second etching process to remove part of the barrier layer. Preferably, the second etching process comprises a non-plasma etching process.

Abstract: A diode device and manufacturing method thereof are provided. The diode device includes a substrate, an epitaxial layer, a trench gate structure, a Schottky diode structure and a termination structure. An active region and a termination region are defined in the epitaxial layer. The Schottky diode structure and the trench gate structure are located in the active region and the termination structure is located in the termination region. The termination structure includes a termination trench formed in the epitaxial layer, a termination insulating layer, a first spacer, a second spacer and a first doped region. The termination insulating layer is conformingly formed on inner walls of the termination trench. The first and second spacers are disposed on two sidewalls of the termination trench. The first doped region formed beneath the termination trench has a conductive type reverse to that of the epitaxial layer.

Abstract: An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

Abstract: A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions.

Abstract: A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.

Abstract: An optical device including a shaped electrode on a substrate thereof utilizes total internal reflection to provide improved transmission of electromagnetic radiation (‘light’) to the substrate compared to standard electrode designs that involve flat electrode surfaces. Redirection of incident light by a tilted or otherwise shaped contact or material added on the contact provides otherwise reflected light to an open surface region of the substrate. Optional plasmon mediated focusing of incident p-polarized light may be realized.

Abstract: A method of fabricating a semiconductor device comprises forming a dielectric layer above a substrate, the dielectric layer including a fixed dielectric portion and a proof mass portion, forming a source region and a drain region in the substrate, forming a gate electrode in the proof mass portion, and releasing the proof mass portion, such that the proof mass portion is movable with respect to the fixed dielectric portion and the gate electrode is movable with the proof mass portion relative to the source region and the drain region.

Abstract: A method for manufacturing an embedded flash memory device is provided. Memory and logic shallow trench isolation (STI) regions respectively extend into memory and logic regions of a substrate. The memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the substrate. A capping layer is formed overlying the logic region. A first etch is performed into the pad layer to expose memory gaps between the memory STI regions. A floating gate layer is formed filling the memory gaps. A second, dry etch is performed into the floating gate layer to etch the floating gate layer back to below upper surfaces of the capping layer and the memory STI regions. A third etch is performed into the memory STI regions to recess the memory STI regions. A fourth etch is performed into the floating gate layer to form floating gates.

Abstract: According to an embodiment, a semiconductor memory device includes first and second stacked bodies, first and second memory parts, and an insulating part. The first stacked body includes first conductive layers and first insulating layers alternately arranged in a first direction. The second stacked body includes second conductive layers and second insulating layers alternately arranged in the first direction. The first and second memory parts extend through the first and second stacked body in the first direction, respectively. The insulating part is provided between the first and second stacked bodies. The insulating part includes a first oxygen-containing film including silicon and oxygen, and a nitrogen-containing film including silicon and nitrogen. The first oxygen-containing film is provided between at least one of first conductive layers and the nitrogen-containing film. The first oxygen-containing film has a hole.

Abstract: In a solid-state imaging device, a photoelectric conversion unit, a transfer transistor, and at least a part of electric charge holding unit, among pixel constituent elements, are disposed on a first semiconductor substrate. An amplifying transistor, a signal processing circuit other than a reset transistor, and a plurality of common output lines, to which signals are read out from a plurality of pixels, are disposed on a second semiconductor substrate.

Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.

Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

Abstract: A radiation detector has a semiconductor substrate of a first conductivity type, a plurality of semiconductor regions of a second conductivity type making junctions with the semiconductor substrate, and a plurality of electrodes joined to the corresponding semiconductor regions. The electrodes cover the corresponding semiconductor regions, when viewed from a direction perpendicular to a first principal face. The semiconductor regions include a plurality of first and second semiconductor regions in a two-dimensionally array. The first semiconductor regions arrayed in a first direction in the two dimensional array out of the plurality of first semiconductor regions are electrically connected to each other, and the second semiconductor regions arrayed in a second direction intersecting with the first direction out of the plurality of second semiconductor regions are electrically connected to each other.

Abstract: The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes transferring a continuous second layer, forming a third layer, and removing the second layer. The second layer is transferred onto a first layer. The first layer has a first opening. The second layer covers the first opening to form a first air gap. The third layer is formed on the first layer. The third layer has a second opening. The second opening is positioned on the first air gap. The second layer is removed through the second opening.

Abstract: A pixel cell includes a storage transistor disposed in a semiconductor substrate. The storage transistor includes a storage gate disposed over the semiconductor substrate, and a storage gate implant that is annealed and has a gradient profile in the semiconductor substrate under the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate. A transfer transistor is disposed in the semiconductor substrate and is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. The transfer transistor includes a transfer gate disposed over the semiconductor substrate. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a read out node. The output transistor includes an output gate disposed over the semiconductor substrate.