Abstract: A tape carrier package with a widow that is capable of confirming an alignment extent between the tape carrier package and a print wiring board in bonding the tape carrier package mounted with an integrated circuit on the liquid crystal panel and the print wiring board. In the package, the integrated circuit is mounted onto a base film. Input pads are connected to the integrated circuit and formed on the base film. Dummy pads are formed at the left and right side thereof not to be connected to the integrated circuit. Windows are provided by opening the base film adjacent to the dummy pads to expose at least two of said dummy pads.

Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

Abstract: A semiconductor chip includes a semiconductor substrate, terminals of A (A is an integer equal to or larger than two groups that are included in each of groups, and an integrated circuit. A plurality of terminals in each of the groups are arranged in accordance with predetermined basic terminal arrangement. Each of the A groups is disposed at each of positions that are defined by rotating one of the positions around a point. Each of the groups includes same-function terminals Vdd (Vss, OE, and WE) to achieve the same function at the same positions of the basic terminal arrangement to enable the same semiconductor chips to be stacked.

Abstract: A substrate layer is provided at the rear side of a single semiconductor element. An active layer is arranged between the substrate layer and a contact side of the single semiconductor element. At least two solder contacts are electrically connected to the active layer and project beyond the contact side in order to make possible a direct soldering of the single semiconductor element to a carrier board. The contact side is provided with a glass passivation layer. Alternatively or additionally to this, at least one side face of the single semiconductor element is provided with an insulator layer in order to avoid short circuits on the soldering of the single semiconductor element to the carrier board. It is furthermore possible for the solder contacts to have different outlines at the contact side.

Abstract: A method for manufacturing a magnetic field detecting element having a soft magnetic core formed on a substrate, first and second coils, each having coil lines, arranged above and below the core, the method including forming a seed film on the substrate, removing a portion of the seed film using a predetermined pattern so that coil lines constituting the first coil subsequently formed on the seed film are separated, forming a first plating mold having grooves corresponding to the predetermined pattern on an upper portion of the seed film, forming coil lines constituting the first coil by filling the grooves of the first plating mold with metal, forming the soft magnetic core and the second coil on an upper portion of the substrate and on the seed film where the first coil is formed, and cutting off edges of the substrate so that the separated coil lines are insulated.

Abstract: A semiconductor device includes a thyristor having at least one body region thereof disposed in a substrate, and a filled trench having a conductive material. According to an example embodiment of the present invention, a conductive material having a narrow upper portion over a relatively wide lower portion is in a filled trench adjacent to at least one thyristor body region in a substrate. In one implementation, a thyristor control port is located over the wide lower portion and adjacent to the narrow upper portion of the conductive shunt and is adapted for capacitively coupling to the thyristor body region in the substrate for controlling current in the thyristor. In another implementation, the conductive material is electrically coupled to a buried emitter region of the thyristor and arranged for shunting current between the buried emitter region and a circuit node near an upper portion of the conductive material.

Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g., in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate.

Abstract: The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.

Abstract: In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

Abstract: The present invention is an electronic interconnect comprising a bond pad consisting essentially of aluminum and copper and configured for use in semiconductor electronic devices to couple a bond wire to an integrated circuit package. The bond pad has an oxide coating residing on at least a topmost surface of the bond pad. The oxide coating consists essentially of aluminum, copper, and oxygen. Therefore, the bond pad has little, if any, naturally occurring corrosion products such as hydrated aluminum hydroxide (Al(OH)3) and/or Al2Cu particles. Al(OH)3 films and Al2Cu particles have been shown to form on aluminum copper bond pads, preventing effective wire-bonding.

Abstract: A diamond composite heat spreader having a variable thermal conductivity gradient can improve control of heat transfer based on a specific application. A diamond-containing region of the heat spreader can contain diamond particles such that the diamond concentration and/or the diamond particle size a varied to produce a desired thermal conductivity gradient. Regions proximate to a heat source can have a higher thermal conductivity than regions further away from the heat source. Thin diamond films can also be used in conjunction with the particulate diamond in order to provide a region of maximum thermal conductivity adjacent a heat source.

Abstract: A heat spreader including a plurality of carbonaceous particles present in an amount of at least about 50% by volume of the heat spreader. A non-carbonaceous infiltrant is also present in an amount of at least about 5% by volume of the heat spreader, the non-carbonaceous infiltrant including an element selected from the group consisting of Cu, Al and Ag. In another aspect, the carbonaceous particles may be sintered or fused directly to one another. The heat spreader can be incorporated into a cooling unit for transferring heat away from a heat source, which includes a heat sink with the heat spreader disposed in thermal communication with both the heat sink and the heat source.

Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Abstract: A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

Abstract: A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

Abstract: The present invention relates to the field of a semiconductor device having a ferroelectric material capacitor and method of making the same. The semiconductor device includes a capacitor having a triple-level oxygen barrier layer pattern formed by an oxygen barrier metal layer, a material layer formed of a conductive solid solution by compounding the oxygen barrier metal layer and oxygen, and an oxygen barrier metal on an interlayer dielectric with a contact plug. The capacitor also has an electrode and a ferroelectric film electrically contacting to the oxygen barrier layer. Further, a wetting layer is formed between the oxygen barrier layer and the contact plug, and an iridium oxygen layer is formed between the oxygen barrier layer and a capacitor electrode.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells.

Abstract: The present invention includes a residue-free overlay target, as well as a method of forming a residue-residue free overlay target. The residue-free overlay target of the present invention is defined by trenches or pads including a series of raised lines. The raised lines included in the overlay target of the present invention substantially eliminate any surface topography, such as depressions, at the top surface of overlying material layers, and, thereby, prevent accumulation of process residue which may obscure the overlay target and inhibit further processing. The method of the present invention may be accomplished and modified using process technology known in the semiconductor fabrication art and includes providing a semiconductor substrate, depositing a resist layer, patterning the resist, and executing a wet or dry etch to create at least one overlay target according to the present invention.