Abstract: An integrated circuit structure includes a semiconductor chip, which further includes a first surface; and a patterned bond pad exposed through the first surface. The patterned bond pad includes a plurality of portions electrically connected to each other, and at least one opening therein. The integrated circuit further includes a dielectric material filled into at least a portion of the at least one opening.

Abstract: It is an object of the present invention to obtain a photoelectric conversion device having a favorable spectral sensitivity characteristic and no variation in output current without such a contamination substance mixed into a photoelectric conversion layer or a transistor. Further, it is another object of the present invention to obtain a highly reliable semiconductor device in a semiconductor device having such a photoelectric conversion device.

Abstract: A audio test method for decreasing noise influence, which includes the following steps: obtaining analog signals; converting the analog signals into digital signals; intercepting digital signals of a first predetermined length and executing a first Fast Fourier Transform (FFT), then obtaining an first Fourier spectrum; recording the amplitudes of frequency values of the first Fourier spectrum; intercepting digital signals of a second predetermined length and executing the second FFT, then obtaining an second Fourier spectrum; recording the amplitudes of the frequency values belonging to odd points of the second frequency spectrum, which are the amplitudes of the noise composition; subtracting the amplitudes of the noise composition from the amplitudes of frequency values of the first Fourier spectrum and obtaining a frequency domain signals without noise composition; executing inverse Fast Fourier Transform (iFFT) for the frequency domain signals and obtaining time domain signals, testing each parameter of th

Abstract: A display device includes an insulating substrate; a plurality of gate wires formed on the insulating substrate, the plurality of gate wires including a gate electrode; a gate insulating layer covering the plurality of gate wires; a transparent electrode layer formed on the gate insulating layer, the transparent electrode layer including a source electrode and a drain electrode disposed about the gate electrode and spaced apart from each other to define a channel region disposed therebetween; a plurality of data wires covering a predetermined portion of the transparent electrode layer and being crossed insulatedly with the plurality of gate wires to define pixels; and an organic semiconductor layer formed on the channel region for each pixel, a predetermined portion of the organic semiconductor layer being operatively connected with the source electrode, the drain electrode, and the gate electrode to form a transistor having an improved characteristic and a novel structure.

Abstract: A display apparatus including a TFT array substrate on which TFTs are formed in an array, a counter substrate disposed so as to face the TFT array substrate, and a sealing pattern for adhering the TFT array substrate and the counter substrate to each other, wherein the counter substrate has a counter electrode, and the TFT array substrate has a first conductive layer, a first insulating film formed on the first conductive layer, a second conductive layer disposed so as to intersect the first conductive layer via the first insulating film, a second insulating film formed on the second conductive layer and having at least two layers, and common electrode wiring provided below the sealing pattern and electrically connected to the counter electrode by the sealing pattern, and the sealing pattern overlaps the second conductive layer via the second insulating film.

Abstract: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on part of the first conductive film to form a gate electrode layer; a second resist mask is formed; third etching is performed to form a source and drain electrode layers, a source and drain regions, and a semiconductor layer; a second insulating film is formed; an opening portion is formed in the second insulating film to partially expose the source or drain electrode layer; a pixel electrode is selectively formed in the opening portion and over the second insulating film; and a supporting portion formed using the gate electrode layer is formed in a region overlapping with the opening portion.

Abstract: A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A RuXTiYOZ film is included in at least one of the bottom and top electrodes, where x, y and z are positive real numbers. A method of fabricating the capacitor through a sequential formation of a bottom electrode, a dielectric layer and a top electrode over a substrate includes forming a RuXTiYOZ film during a formation of at least one of the bottom electrode and top electrode, where x, y and z are positive real numbers.

Abstract: A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

Abstract: Semiconductor devices are provided including a semiconductor substrate and a first interlayer insulating layer on the semiconductor substrate. A contact pad is provided in the first interlayer insulating layer and a second insulating layer is provided on the first interlayer insulating layer. A contact hole is provided in the second interlayer insulating layer. The contact hole exposes the contact pad and a lower portion of the contact hole has a protrusion exposing the contact pad. The protrusion is provided on the second interlayer insulating layer. A contact spacer is provided on inside sidewalls of the contact hole and fills the protrusion. A contact plug is provided in the contact hole. Related methods are also provided herein.

Abstract: The semiconductor device includes a plurality of semiconductor chips, and a circuit substrate having a substantially rectangular outer shape. The semiconductor device is an MCM having an MCM packaging structure in which the plurality of semiconductor chips are juxtaposed on the semiconductor chip mounting surface of the circuit substrate, and the semiconductor chip mounting surface is covered by a sealing resin along an outer edge of the circuit substrate so that the plurality of semiconductor chips are sealed.

Abstract: A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

Abstract: A nonvolatile semiconductor memory device has a cell which includes a drain diffusion region and a source diffusion region formed on a surface layer of a semiconductor substrate; a first insulating film formed between the source diffusion region and the drain diffusion region; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; a first control gate formed on the second insulating film; a third insulating film formed on the first control gate and a sidewall thereof and on a sidewall of the floating gate; and a second control gate formed on the first control gate with the third insulating film interposed therebetween.

Abstract: A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

Abstract: A transistor switch for a system operating at high frequencies is provided. The transistor switch comprises a graded channel region between a source region and a drain region, the graded channel region configured for providing a low resistance to mobile negative charge carriers moving from the source region to the drain region, wherein the graded channel comprises at least two doping levels.

Abstract: As disclosed herein, an FEOL line conductor stack is formed including a base conductor layer, an overlying layer of tungsten, and an optional gate capping layer. The stack, including layers from the optional capping layer down to the base conductor layer are directionally etched until an underlying layer is exposed. Then, the substrate is exposed to one or the other or both of: 1) a silicon-containing ambient to form a self-aligned layer of tungsten silicide on sidewalls of the tungsten layer; and 2) a source of nitrogen to form a thin layer of tungsten nitride on sidewalls of the tungsten layer. Such tungsten silicide and/or tungsten nitride layers serves to protect the tungsten during subsequent processing, among which may include sidewall oxidation (e.g. for a polysilicon base conductor layer) and/or the forming of silicon nitride spacers on sidewalls of the gate stack.

Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

Abstract: A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.

Abstract: A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

Abstract: A microelectromechanical system switch may be formed with a protrusion defined on the substrate which makes contact with a deflectable member arranged over the substrate. The deflectable member may, for example, be a cantilevered arm or a deflectable beam. The protrusion may be formed in the substrate in one embodiment using field oxide techniques.

Abstract: A power device includes a substrate assembly including an upper surface and a lower surface. The substrate assembly includes a first layer and a second layer. The first layer overlies the second layer and has different conductivity than the second layer. A first electrode is provided proximate the upper surface. A second electrode is provided proximate the upper surface and is spaced apart from the first electrode. The second layer is configured to provide a current path between the first and second electrodes.