Patents Examined by Mark W Tornow
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Patent number: 11984531Abstract: Provided is a light emitting device. A light emitting device includes a first n-type semiconductor layer, a first light emitting layer disposed on the first n-type semiconductor layer, a first p-type semiconductor layer disposed on the first light emitting layer, a second p-type semiconductor layer disposed on the first p-type semiconductor layer, a bonding layer disposed between the first p-type semiconductor layer and the second p-type semiconductor layer, a second light emitting layer disposed on the second p-type semiconductor layer, a second n-type semiconductor layer disposed on the second light emitting layer, a p-type electrode disposed on the second p-type semiconductor layer, a first n-type electrode disposed on the first n-type semiconductor layer, and a second n-type electrode disposed on the second n-type semiconductor layer.Type: GrantFiled: June 22, 2021Date of Patent: May 14, 2024Assignee: LG DISPLAY CO., LTD.Inventors: KooHwa Lee, WooNam Jeong, HyeonHo Son
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Patent number: 11978833Abstract: The present invention provides a white light LED package structure and a white light source system, which includes a substrate, an LED chip, and a wavelength conversion material layer. The peak emission wavelength of the LED chip is between 400 nm and 425 nm; the peak emission wavelength of the wavelength conversion material layer is between 440 nm and 700 nm, and the wavelength conversion material layer absorbs light emitted from the LED chip and emits a white light source; and the emission spectrum of the white light source is set as P(?), the emission spectrum of a blackbody radiation having the same color temperature as the white light source is S(?), P(?max) is the maximum light intensity within 380-780 nm, S(?max) is the maximum light intensity of the blackbody radiation within 380-780 nm, D(?) is a difference between the spectrum of the white light LED and the spectrum of the blackbody radiation, and within 510-610 nm, the white light source satisfies: D(?)=P(?)/P(?max)?S(?)/S(?max), ?0.Type: GrantFiled: December 1, 2021Date of Patent: May 7, 2024Assignee: QUANZHOU SANAN SEMICONDUCTOR TECHNOLOGY CO., LTD.Inventors: Senpeng Huang, Junpeng Shi, Weng-Tack Wong, Shunyi Chen, Zhenduan Lin, Chih-wei Chao, Chen-ke Hsu
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Patent number: 11973110Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.Type: GrantFiled: May 6, 2021Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Che-Yuan Chang, Hui-Zhong Zhuang, Chih-Liang Chen
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Patent number: 11968839Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.Type: GrantFiled: September 6, 2022Date of Patent: April 23, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Yanli Zhang, Johann Alsmeier
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Patent number: 11955520Abstract: According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member includes a first nitride region including Alx1Ga1-x1N (0<x1?1), a second nitride region including Alx2Ga1-x2N (0<x2<1, x2<x1), and a third nitride region. The second nitride region is between the first nitride region and the third nitride region. The third nitride region includes Al, Ga, and N. The third nitride region does not include carbon, alternatively a third carbon concentration in the third nitride region is lower than a second carbon concentration in the second nitride region.Type: GrantFiled: July 8, 2021Date of Patent: April 9, 2024Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Hikosaka, Hajime Nago, Jumpei Tajima, Shinya Nunoue
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Patent number: 11948922Abstract: A display apparatus includes a display substrate, and light emitting devices arranged on an upper surface of the display substrate. At least one of the light emitting devices includes a first LED unit including a first light emitting stack, a second LED unit including a second light emitting stack, and a third LED unit including a third light emitting stack. The second LED unit is disposed between the first LED unit and the third LED unit. Each of the first to third light emitting stacks includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. The first conductivity type semiconductor layer and the second conductivity type semiconductor layer in each of the first to third light emitting stacks are stacked in a horizontal direction with respect to the upper surface of the display substrate.Type: GrantFiled: December 28, 2020Date of Patent: April 2, 2024Assignee: Seoul Viosys Co., Ltd.Inventors: Chung Hoon Lee, So Ra Lee
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Patent number: 11943972Abstract: The present disclosure provides a display panel and a manufacturing method thereof, which include a flexible substrate, an array layer, a pixel definition layer, an insulating layer, a light-emitting layer, an additional layer, and a first inorganic layer. The array layer, the pixel definition layer, and the insulating layer are sequentially disposed on the flexible substrate, the insulating layer includes first through holes and second through holes, the light-emitting layer is filled in the first through holes, and the additional layer is disposed on the pixel definition layer, in the second through holes, and on the insulating layer and the light-emitting layer. The first inorganic layer is disposed on the array layer and the additional layer.Type: GrantFiled: June 17, 2020Date of Patent: March 26, 2024Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Jiajia Sun
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Patent number: 11943934Abstract: The present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within one or more stacked inter-level dielectric (ILD) layers over a substrate. An etch stop structure is disposed over the one or more lower interconnect layers and a bottom electrode is disposed over the etch stop structure. The bottom electrode electrically contacts the one or more lower interconnect layers. A magnetic tunnel junction (MTJ) stack is disposed over the bottom electrode. The MTJ stack has sidewalls arranged at a first angle with respect to a bottom surface of the MTJ stack. A top electrode is disposed over the MTJ stack. The top electrode has sidewalls arranged at a second angle with respect to a bottom surface of the top electrode. The second angle is greater than the first angle.Type: GrantFiled: June 30, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chern-Yow Hsu
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Patent number: 11942330Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include flowing a first reagent in a substrate processing region housing the semiconductor substrate. The first reagent may include HX. X may be at least one of fluorine, chlorine, and bromine. The semiconductor substrate may include an exposed region of gallium oxide. Fluorinating the exposed region of gallium oxide may form a gallium halide and H2O. The methods may include flowing a second reagent in the substrate processing region. The second reagent may be at least one of trimethylgallium, tin acetylacetonate, tetramethylsilane, and trimethyltin chloride. The second reagent may promote a ligand exchange where a methyl group may be transferred to the gallium halide to form a volatile Me2GaY or Me3Ga. Y may be at least one of fluorine, chlorine, and bromine from the second reagent. The methods may include recessing a surface of the gallium oxide.Type: GrantFiled: June 9, 2022Date of Patent: March 26, 2024Assignee: Applied Materials, Inc.Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly
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Patent number: 11935894Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.Type: GrantFiled: November 4, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
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Patent number: 11937481Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate and a white OLED display unit on the base substrate, and further includes: an optical adjustment structure on a light emitting side of the white OLED display unit, where the optical adjustment structure is in a peripheral region of each pixel region. The optical adjustment structure is configured to absorb light in a first wavelength range or convert light in a first wavelength range into light in a second wavelength range.Type: GrantFiled: April 9, 2020Date of Patent: March 19, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Guang Yan, Changyen Wu, Linlin Wang, Yongqi Shen, Juanjuan You, Li Sun
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Patent number: 11935984Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.Type: GrantFiled: December 14, 2022Date of Patent: March 19, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Seok Han, Sung Woo Kim, Jin A Kim, Tae Hyung Kim, Kun Su Park, Yuho Won, Jeong Hee Lee, Eun Joo Jang, Hyo Sook Jang
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Patent number: 11937446Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel the peripheral circuit is in the peripheral circuit region.Type: GrantFiled: October 21, 2019Date of Patent: March 19, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xinwei Gao, Kaihong Ma, Dacheng Zhang, Lang Liu, Chen Xu
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Patent number: 11935907Abstract: Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.Type: GrantFiled: June 21, 2021Date of Patent: March 19, 2024Assignee: Adeia Semiconductor Technologies LLCInventor: Rajesh Katkar
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Patent number: 11929418Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.Type: GrantFiled: November 11, 2021Date of Patent: March 12, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
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Patent number: 11923399Abstract: A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer.Type: GrantFiled: March 31, 2021Date of Patent: March 5, 2024Assignee: PlayNitride Display Co., Ltd.Inventors: Sheng-Yuan Sun, Loganathan Murugan, Po-Wei Chiu, Yun-Li Li
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Patent number: 11923417Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.Type: GrantFiled: March 11, 2022Date of Patent: March 5, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Hong Yu, Shesh Mani Pandey
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Patent number: 11923482Abstract: A light emitting device and method of forming a light emitting device are disclosed. The light emitting device includes a light emitting diode and a phosphor layer formed on the light emitting diode, the phosphor layer including a plurality of phosphor particles formed in a particle layer, the particle layer including interstices between the phosphor particles, and a matrix material disposed in a portion of the interstices. A plurality of cavities may be disposed in a remaining portion of the interstices.Type: GrantFiled: September 29, 2020Date of Patent: March 5, 2024Assignee: Lumileds LLCInventors: Joerg Feldmann, Marcel Rene Bohmer, Marinus Johannes Petrus Maria van Gerwen, Yu-Chen Shen
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Patent number: 11916049Abstract: A LED light display having a plurality of LED bulb arrays and a louver panel defining a plurality of hole arrays. Each hole array can define openings that are sized and spaced to receive at least the distal end portions of the bulbs forming a single LED bulb array. The louver panel further has a plurality of shaped protrusions in the form of louvers that are configured to extend outwardly and forwardly from a front surface of the louver panel and are arranged in a plurality of columns and in a plurality of rows in regularly repeating patterns related to the pattern of the placement of a plurality of the plurality of hole arrays in the louver panel and are further configured to block at least a portion of the emission of light from the LED bulbs in both a horizontal and vertical direction.Type: GrantFiled: December 13, 2022Date of Patent: February 27, 2024Assignee: Formetco, Inc.Inventor: Jim Shimmin
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Patent number: 11908979Abstract: A photocurable composition includes quantum dots, quantum dot precursor materials, a chelating agent, one or more monomers, and a photoinitiator. The quantum dots are selected to emit radiation in a first wavelength band in the visible light range in response to absorption of radiation in a second wavelength band in the UV or visible light range. The second wavelength band is different than the first wavelength band. The quantum dot precursor materials include metal atoms or metal ions corresponding to metal components present in the quantum dots. The chelating agent is configured to chelate the quantum dot precursor materials. The photoinitiator initiates polymerization of the one or more monomers in response to absorption of radiation in the second wavelength band.Type: GrantFiled: September 1, 2022Date of Patent: February 20, 2024Assignee: Applied Materials, Inc.Inventors: Yingdong Luo, Daihua Zhang, Hou T. Ng, Sivapackia Ganapathiappan, Nag B. Patibandla