Abstract: A micro-LED display panel includes a substrate, an insulating layer on the substrate, and a plurality of micro-LEDs on the substrate and embedded in the insulating layer. The micro-LEDs define a display area. Each micro-LED includes a bottom surface coupled to a lower electrode and a top surface exposed from the insulating layer and coupled to the upper electrode. Conductive blocks are set outside the display area, the conductive blocks are electrically coupled to a driving circuit on the substrate. Top wires are set on a surface of the insulating layer away from the substrate and each top wire is electrically coupled to at least one upper electrode and at least one conductive block.

Abstract: The disclosure provides a display device. The display device includes a substrate, a transistor, an insulating layer, a light blocking layer, a light emitting element, and a light conversion element. The transistor is disposed on the substrate. The insulating layer is disposed on the substrate. The insulating layer includes at least one opening. The light blocking layer is disposed on a top surface of the insulating layer and at least partially overlapped with the transistor. The light emitting element is disposed in the at least one opening, and the light emitting element includes an electrode electrically connected to the transistor. The light conversion element is disposed on the light emitting element.

Abstract: The disclosure describes various aspects of strain management layers for light emitting elements such as light-emitting diodes (LEDs). The present disclosure describes an LED structure formed on a substrate and having a strain management region supported on the substrate, and an active region configured to provide a light emission associated with the LED structure. The strain management region includes a first layer including a superlattice having a plurality of repeated first and second sublayers, and a second layer including a bulk layer. In an embodiment, at least one of the first and second sublayers and the bulk layer includes a composition of InxAlyGa1-x-yN. A device having multiple LED structures and a method of making the LED structure are also described.

Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

Abstract: Light-emitting diodes (LEDs), and more particularly edge structures for light shaping in LED chips are disclosed. Edge structures may include a repeating pattern of features that is formed along one or more mesa sidewalls of active LED structure mesas. Such active LED structure mesas may include a p-type layer, an active layer, and at least a portion of an n-type layer. Features of the repeating pattern may be configured with a size and/or shape to promote redirection of laterally propagating light from the active layer at the mesa sidewalls. In this manner, light that may otherwise escape the LED chip at the mesa sidewalls may be redirected toward an intended emission direction for the LED chip. Certain aspects include reflective structures that are provided on the active LED structures mesas and are further arranged to extend past the active LED structure mesas to cover the repeating pattern of features.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively.

Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.

Abstract: Provided is a display module including a substrate including a mounting surface, a side surface, and a chamfer portion formed between the mounting surface and the side surface, a plurality of inorganic light emitting diodes mounted on the mounting surface and each including a pair of electrodes electrically connected to the substrate, a black matrix arranged between the plurality of inorganic light emitting diodes, and a cover bonded to the mounting surface and configured to cover the mounting surface, wherein the pair of electrodes are oriented in a direction opposite to a direction in which the plurality of inorganic light emitting diodes emits light, and the cover is provided to extend outward of the side surface in an extension direction of the mounting surface.

Abstract: A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between corresponding ends of remnant portion of gate patterns are expanded.

Abstract: The present disclosure provides a display apparatus, a display panel and a method for manufacturing the same. The display panel includes a substrate including a display area including a plurality of sub-pixels, and a gate driving area including a gate driving circuit, a first buffer layer contacting the substrate in the gate driving area, a second thin film transistor disposed in the gate driving area while including a second semiconductor layer made of a second semiconductor, a second buffer layer disposed at a first opening exposing the substrate in the display area while contacting the substrate, and a first thin film transistor disposed at the first opening in the display area while including a first semiconductor layer made of a first semiconductor different from the second semiconductor.

Abstract: A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.

Abstract: A nitride-based light-emitting diode (LED) device includes an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, a p-type nitride semiconductor layer disposed on the active layer, and a defect control unit disposed between the n-type nitride semiconductor layer and the active layer. The defect control unit includes first, second and third defect control layers that are sequentially disposed on the n-type nitride semiconductor layer, and that have different doping concentrations. The third defect control layer includes one of Al-containing ternary nitride, Al-containing quaternary nitride, and a combination thereof.

Abstract: Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.

Abstract: A light emitting device including first, second, and third light emitting stacks each including first and second conductivity type semiconductor layers, a first lower contact electrode in ohmic contact with the first light emitting stack, and second and third lower contact electrodes respectively in ohmic contact with the second conductivity type semiconductor layers of the second and third light emitting stacks, in which the first lower contact electrode is disposed between the first and second light emitting stacks, the second and third lower contact electrodes are disposed between the second and third light emitting stacks, the first, second, and third lower contact electrodes include transparent conductive oxide layers, and a thickness of the second lower contact electrode or the third lower contact electrode is greater than a thickness of the first lower contact electrode.

Abstract: The forming method of a flip-chip light emitting diode structure includes the following steps. A first substrate including a first semiconductor layer, an active layer on the first semiconductor layer and a second semiconductor layer on the active layer is provided. A first current blocking layer is formed on the second semiconductor layer, in which the first current blocking layer has a plurality of interspaces. A reflective layer covering the interspaces is formed, in which the reflective layer has a plurality of recesses, and each of the recesses is corresponding to each of the interspaces. A second current blocking layer filling into the recesses is formed.

Abstract: A manufacturing method of a fin semiconductor device comprises: providing a substrate, wherein a fin channel base is patterned on and in contact with the substrate; epitaxially growing a top part of the fin channel base and extending the top part of the fin channel base sideways and upward to form a fin channel core; oxidizing the fin channel base to form a fin channel structure, wherein the fin channel structure comprises the fin channel core surrounded with an oxide layer at the top part of the fin channel base and an intermediate part of the fin channel base under the top part; and removing the oxide layer to expose the fin channel core, wherein the fin channel core suspends over the substrate.

Abstract: A semiconductor element includes a plurality of microlenses provided on a main surface to collect light, a plurality of conductive electrodes provided on a back surface of the main surface, a photoelectric converter to which the light collected by the plurality of microlenses is guided, and a strain sensor provided on the same layer as the photoelectric converter to detect a strain. A solid-state imaging apparatus includes the semiconductor element, a transparent member, an adhesive layer that covers the plurality of microlenses and adheres to the transparent member, and a plurality of external connection electrodes electrically connected to the plurality of conductive electrodes, respectively.

Abstract: A semiconductor structure formation method and a mask are provided.