Abstract: Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.

Abstract: Techniques test a storage system. Such techniques involve: acquiring a result of performing a first test on the storage system using a test case; if the result indicates that the storage system fails the first test, performing a second test on the storage system based on a problem of the storage system; and if the result indicates that the storage system passes the first test, determining a security level of the test case based on the result. Such techniques can effectively enhance test performance and system reliability of the storage system.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices.

Abstract: A method for identifying outlier devices during testing, includes: establishing binning limits for a device being tested based on one or more rules generated from external test results data of tests involving similar devices; receiving test results data in real time for the device being tested while the device is on a device tester; applying the one or more rules to the test results data for the device in real time; determining in real time, based on results of applying the one or more rules to the test results data, whether the device is an outlier with respect to the binning limits; and in response to determining that the device is an outlier, binning the outlier device separately from tested devices having test results data falling within the binning limits.

Abstract: Provided are a Cyclic Redundancy Check (CRC) circuit, and a method and an apparatus thereof, a chip and an electronic device, which belong to the technical field of computers. Herein, the cyclic redundancy check circuit may include: a configuration module configured to acquire configuration information and an information field, a CRC arbitration module configured to determine a generator polynomial according to the configuration information, a CRC control module configured to respond to triggering of the CRC arbitration module and output a clock signal, a coefficient corresponding to each power in the generator polynomial and the information field, a parallel iteration module configured to respond to the clock signal and implement parallel iteration for the information field according to the coefficient corresponding to the each power in the generator polynomial, as to output an iteration result, and a CRC output module configured to package the information field according to the iteration result.

Abstract: According to certain embodiments, a method for use in a transmitter comprises selecting an information set or sequence of information sets for polar encoding. The information set or sequence of information sets are selected from a plurality of information sets based on one or more system parameters and/or one or more link measurements. The method further comprises performing polar encoding for a plurality of data bits to yield encoded data. The polar encoding is performed according to the selected information set or sequence of information sets. The method further comprises transmitting the encoded data to a receiver.

Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

Abstract: A method and apparatus for masking errors in a DRAM write are disclosed to perform a partial write request with an SSD controller. In embodiments, write data from a host is provided to the controller that is not aligned to the DRAM data. The controller issues a read command from the LBA of a data storage device, and a corresponding write command to write the data received from the host, prior to receipt of the read data, to perform a partial write. The read data is error corrected, and in the event an error is found in the read data, bytes containing an error are masked. The read data, including masked read data, and write data are merged to form partial write data, and written to the DRAM. In certain embodiments, the partial write data may be provided to a logic analyzer to assess the masked read data for debug analysis.

Abstract: A computing system is disclosed. The computing system includes a computation unit, one or more processors, a volatile memory, and a non-volatile memory communicatively coupled to the one or more processors and having instructions stored thereon, which when executed by the one or more processors, causing the one or more processor to instantiate a container and perform at least one of a volatile memory checking procedure or a non-volatile memory checking procedure. The volatile memory checking procedure includes checking the first physical address space for errors, loading a container into volatile memory containing the first physical address space if an error is determined, rechecking the first physical address space for error, loading the container to a second physical address space and updating a memory management unit if an error in the first physical address space is determined.

Abstract: Provided is a coding unit to determine the number of code block groups, divide an input bit sequence to code block segmentation into code block groups of the number of the code block groups, determine the number of code blocks for each of the code block groups, divide each of the code block groups into code blocks of the number of the code blocks, and apply channel coding to each of the code blocks.

Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

Abstract: A method comprising: identifying, by a resource manager, a resource of a storage system, the resource being one which a testing system lacks permission to use for testing the storage system; adding, by the resource manager, the resource to a group of resources which the testing system is permitted to use for testing the storage system, wherein adding the resource to the group includes granting the testing system a temporary permission to use the resource for testing the storage system; allocating the resource to a test that is performed by the testing system; and removing, by the resource manager, the resource from the group wherein removing the resource from the group includes revoking the temporary permission.

Abstract: A method for determining the n best positions of frozen bits in a channel decoder for a noisy communication channel. A decoding method and decoding processing unit for implementing the channel having frozen bits at the n worst positions. A method and system that iteratively, for each bit i from the n bits, determines a probability vector for the bit i by traversing a logical graph using contraction identities simplified to specific values, indexes the specific values from the contraction identities newly computed during the determination of the probability vector for subsequent reference during a following iteration based on corresponding contraction identities, fixes the bit i from the probability vector and moving to bit i+1 until all n bits are fixed.

Abstract: An access device includes a memory controller coupled to a memory device and configured to access the memory device. The memory controller is further configured to perform a test procedure on the memory device to obtain a test result, write a boot code index, which indicates a predetermined address for storing predetermined system data of the memory device and a copy rule adopted for generating one or more duplicates of the predetermined system data, in the memory device, establish system data of the memory device according to the test result, write the system data into the predetermined address as the predetermined system data, and write the system data in one or more memory blocks of the memory device as the duplicates of the predetermined system data according to the copy rule.

Abstract: Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.

Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

Abstract: Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.

Abstract: Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correction encoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword on a column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.