Abstract: A storage device includes a nonvolatile memory device, a memory controller, and a buffer memory. The memory controller determines a first memory block of the nonvolatile memory device, which is targeted for a read reclaim operation, and reads target data from a target area of the first memory block. The target data are stored in the buffer memory. The memory controller reads at least a portion of the target data stored in the buffer memory in response to a read request corresponding to at least a portion of the target area.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: A memory storage apparatus including a memory array and a controller circuit is provided. The memory array is configured to store a first error correcting code and a first data. The controller circuit is coupled to the memory array. The controller circuit is configured to read the first data from the memory array and determine whether an error bit of the first data is one of one or more data mask bits to decide whether to update the first error correcting code stored in the memory array. The controller circuit includes a switch element. The switch element is coupled to the memory array. The switch element receives the first data from the memory array. An error correcting procedure is not performed on the first data. In addition, a data access method is also provided.

Abstract: Disclosed is a memory system and a method of operating the memory system. The memory system includes a semiconductor memory device configured to read data stored in a selected logical page among a plurality of logical pages by applying different read voltages to a selected word line corresponding to the plurality of logical pages. The memory system also includes a controller configured to perform an operation for detecting and correcting an error of the data whenever each of the read voltages is applied to the selected word line.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: A system and method for erasure coding. The method includes distributing a plurality of data chunks according to a mirroring scheme, wherein the plurality of data chunks is distributed as a plurality of rows among a plurality of non-volatile memory (NVM) nodes, wherein the mirroring scheme defines a plurality of groups, each group including a subset of the plurality of data chunks, wherein each data chunk in a group has a role corresponding to a relative position of the data chunk within the group, wherein data chunks included in the plurality of groups having the same relative positions within their respective groups have the same role, wherein each row of the plurality of rows includes at least one summation data chunk that is a function of at least one data chunk included in the row and of at least one extra data chunk included in at least one other row.

Abstract: [Object] To provide a communication device capable of considerably improving transmission efficiency of an entire system by realizing flexible design in accordance with various use cases in a communication system in which a base station device and a terminal device communicate with each other. [Solution] Provided is the communication device including: a setting unit configured to share information regarding a region specified in accordance with a predetermined pattern, with another device; and a transmission processing unit configured to broadcast HARQ feedback.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for data processing in a communication system. For example, a method comprises pre-processing received data encoded with a polar code; performing a first decoding of the pre-processed data to obtain output bits; in response to decoding failure of the first decoding, bit-flipping a portion of information bits of the output bits to obtain a first additional frozen bit; and performing a second decoding based on the first additional frozen bit and the pre-processed data. Embodiments of the present disclosure further provide a communication device capable of implementing the above method.

Abstract: Encoding System for Incremental Redundancy for Hybrid ARQ for Wireless Networks A technique is provided for encoding, by an outer encoder, a set of information bits; performing, by each polar sub-encoder of a set of polar sub-encoders, polar encoding of bits received from the outer encoder for a corresponding incremental redundancy (IR) hybrid ARQ (HARQ) transmission; and performing, by an inner encoder, for each bit input to the inner encoder from one of the polar sub-encoders for the HARQ transmission, an Exclusive Or (XOR) operation with another bit, to generate a set of code bits for an IR-HARQ transmission over a channel.

Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.

Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Abstract: A reliability evaluation apparatus according to the present embodiment is provided with a housing and a board insertable into the housing. A plurality of sockets are provided on the board. Semiconductor devices are respectively attachable to socket. The plurality of sockets have electrodes electrically connectable to terminals of the semiconductor devices. A heater is provided inside the housing. A controller is connected to the plurality of sockets and to the heater. The controller controls a voltage to be applied to the terminal of the semiconductor device and controls an output of the heater. A plurality of electromagnets are arranged inside the housing so as to be positioned above or below the plurality of sockets when the board is inserted into the housing.

Abstract: A method for scan chain testing a multi-chip module including a plurality of integrated circuit dice, some of the integrated circuit dice being of a first type and some of the integrated circuit dice being of a second type, includes separately applying a first boundary scan test stream to each die of the first type, and a second boundary scan test stream to each die of the second type. Testing apparatus includes a test interface that couples to each respective test access port, and a controller configured to separately apply the first boundary scan test stream to each die of the first type, and the second boundary scan test stream to each die of the second type. A multi-chip module includes a plurality of integrated circuit dice, each having a boundary scan register chain with a test access port, and a test access port for the module as a whole.

Abstract: A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.

Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times.

Abstract: A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.

Abstract: A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.

Abstract: There are provided a memory controller and a memory system including the same. The memory controller includes: a processor for generating a command and an address in response to a request from a host, and generating a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices; a buffer memory for temporarily storing the data, the bin label, and the LLR; and an error correction circuit for performing error correction decoding on the data, using the LLR.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.