Abstract: A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

Abstract: A semiconductor device including a substrate is provided. The device further includes a through-substrate via (TSV) extending into the substrate, and a substantially helical conductor disposed around the TSV. The substantially helical conductor can be configured to generate a magnetic field in the TSV in response to a current passing through the helical conductor. More than one TSV can be included, and/or more than one substantially helical conductor can be provided.

Abstract: A semiconductor device having an LDMOS transistor can include: a first deep well region having a first doping type; a drift region located in the first deep well region and having a second doping type; and a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor.

Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

Abstract: An image sensing device includes a semiconductor substrate, a plurality of photoelectric conversion elements supported by the semiconductor substrate, each photoelectric conversion elements configured to generate an electrical signal corresponding to incident light by performing a photoelectric conversion of the incident light, a plurality of color filters disposed over the semiconductor substrate to filter incident light to be received by the photoelectric conversion elements, each color filter configured to allow light having a specific color to pass therethrough, and a grid structure disposed between the color filters and structured to include asymmetric sidewalls that are shaped based on colors of adjacent color filters.

Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Abstract: An apparatus includes: a memory mat including a plurality of vertical memory cell transistors; a shield structure covering the memory mat and surrounding each of the plurality of vertical memory cell transistors; and a ring-shaped wiring above the shield structure, the ring-shaped wiring being connected to the shield structure in an edge region of the shield structure.

Abstract: A FinFET is provided. The FinFET includes a substrate including an NMOS (N-type metal-oxide-semiconductor) region; a plurality of fins formed on the substrate; an isolation layer formed between adjacent fins of the plurality of fins and on the substrate; a gate structure across a length portion of the fin and covering a portion of each of a top surface and sidewalls of the fin; and an in-situ doped epitaxial layer formed on each of the etched fin on both sides of the gate structure. The doping ions in the in-situ doped epitaxial layer are N-type ions.

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

Abstract: A source pad of a main semiconductor element is electrically connected to an n+-type source region via a barrier metal. A temperature sensing part is a poly-silicon diode formed by a pn junction between a p-type poly-silicon layer that is a p-type anode region and an n-type poly-silicon layer that is an n-type cathode region. The temperature sensing part is provided, via the field insulating film, on a front surface of a same semiconductor substrate as the main semiconductor element. An anode pad and a cathode pad are in direct contact with the p-type poly-silicon layer and the n-type poly-silicon layer, respectively. The source pad, the anode pad, and the cathode pad are aluminum alloy films.

Abstract: A silicon carbide semiconductor device, in particular a monolithically integrated trench Metal-Oxide-Semiconductor Field-Effect Transistor with segmentally surrounded trench Schottky diode, includes a semiconductor substrate, a trench Metal-Oxide-Semiconductor Field-Effect Transistor and a trench Schottky diode. The trench Schottky diode has a perpendicularly disposed trench extending in a first horizontal direction, a metal electrode filled into the trench, and a plurality of doped regions disposed segmentally and extending in a second horizontal direction around the trench. The first horizontal direction is substantially orthogonal to the second horizontal direction, a side wall and a bottom wall of the metal electrode in the trench forms a Schottky junction, and the current flowing from the metal electrode is restricted between adjacent doped regions.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain contacting layer, wherein the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region. The source-drain contacting layer contacts the first doped region and the third doped region. A doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure. Doping type of the first doped region and a doping type of the second doped region are same.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding vires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.

Abstract: A three-dimensional memory device including first and second stacking structures and first and second conductive pillars is provided. The first stacking structure includes first stacking layers stacked along a vertical direction. Each first stacking layer includes a first gate layer, a first channel layer, and a first ferroelectric layer between the first gate and channel layers. The second stacking structure is laterally spaced from the first stacking structure and includes second stacking layers stacked along the vertical direction. Each second stacking layer includes a second gate layer, a second channel layer, and a second ferroelectric layer is between the second gate and channel layers. The first and second gate layers are disposed between the first and second ferroelectric layers, and the first and second conductive pillars extend along the vertical direction in contact respectively with the first and second channel layers.

Abstract: An apparatus includes a base structure having a first portion including a plurality of transistors and a second portion surrounding the first portion; a storage structure on the first portion of the base structure, the storage structure including a plurality of storage capacitors each coupled to a corresponding one of the plurality of transistors; an interface structure on the second portion of the base structure; and a peripheral structure on the interface structure; wherein the interface structure is divided into a plurality of insulating films and the plurality of insulating films are arranged away from each other to have a plurality of voids between the second portion of the base structure and the peripheral structure.