Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

Abstract: An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.

Abstract: The purpose of the present invention is to provide a highly accurate and highly reliable physical quantity sensor wherein an error due to stress applied to a sensor element of the physical quantity sensor is reduced. This physical quantity sensor device is provided with: a hollow section formed in a Si substrate; an insulating film covering the hollow section; and a heating section formed in the insulating film. The sensor device is also provided with a detection element that detects the temperature of the insulating film above the hollow section, the detection element is provided with a first silicon element and a second silicon element, and the first silicon element and the second silicon element are doped with different impurities, respectively.

Abstract: An infrared detector. The detector includes: a superlattice structure including: at least three first layers; and at least three second layers, alternating with the first layers. Each of the first layers includes, as a major component, InAsxP1-x, wherein x is between 0.0% and 99.0%, and each of the second layers includes, as a major component, InAsySb1-y, wherein y is between 0% and 60%.

Abstract: An image sensor includes a device isolation layer disposed in a substrate and defining pixel regions, and a grid pattern on a surface of the substrate. The grid pattern overlaps the device isolation layer between adjacent pixel regions in a direction perpendicular to the surface. The grid pattern has a width less than a width of the device isolation layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.

Abstract: Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can include a first field effect transistor (FET). The semiconductor structure can also include a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.

Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4, constituting an electron transit layer, a second nitride semiconductor layer 5, formed on the first nitride semiconductor layer 4 and constituting an electron supply layer, a nitride semiconductor gate layer 6, disposed on the second nitride semiconductor layer 5 and containing an acceptor type impurity, a metal film 7, formed on the nitride semiconductor gate layer 6, and a gate pad 23, connected to the metal film 7 via a gate insulating film 8 having a first surface and a second surface, the first surface of the gate insulating film 8 is electrically connected directly or via a metal to the metal film 7, and the second surface of the gate insulating film 8 is electrically connected directly or via a metal to the gate pad 23.

Abstract: Disclosed is an electroluminescent display device including a substrate, a first electrode provided on the substrate, a bank configured to cover an end of the first electrode and to define an emission area, and provided with a first receiving groove, an emission layer provided on the first electrode in the emission area defined by the bank, and a light absorbing layer provided in the first receiving groove of the bank, wherein the first receiving groove is formed in the bank, and the light absorbing layer is formed in the first receiving groove so that the external light is absorbed in the light absorbing layer, to thereby prevent the color interference and Haze phenomenon between the neighboring pixels.

Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.

Abstract: A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a nano-scale semiconductor structure. The second electrode is located on the second end.

Abstract: A reactive material erasure element comprising a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Abstract: A transistor and a method for forming the same are provided. The transistor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate includes a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate, a polysilicon layer fixed to the semiconductor substrate, and a silicon nitride layer in contact with the polysilicon layer, wherein the polysilicon layer includes an n-type layer and a p-type layer in contact with the n-type layer; a semiconductor device manufacturing method includes forming the polysilicon layer covering at least one hydrogen-containing layer, and heating the polysilicon layer and the hydrogen-containing layer.

Abstract: A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

Abstract: A compound sensor device includes a semiconductor substrate having an active electronic circuit formed in or on the semiconductor substrate. A sensor including a sensor substrate including a sensor circuit having an environmental sensor or actuator formed in or on the sensor substrate is micro-transfer printed onto the semiconductor substrate. One or more electrical conductors electrically connect the active electronic circuit to the sensor circuit. The semiconductor substrate includes a first material and the sensor substrate includes a second material different from the first material.

Abstract: A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Abstract: A display apparatus includes: a first substrate having a front surface and a rear surface; a first display layer disposed on the front surface of the first substrate, the first display layer configured to emit light in a front direction; a second display layer disposed on the rear surface of the first substrate, the second display layer configured to emit light in a rear direction; and a pressure sensor disposed on the rear surface of the first substrate, the pressure sensor configured to sense a pressure of a touch of a user.

Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.