Abstract: A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

Abstract: A flexible display and a method of manufacturing the same are disclosed. In one aspect, the method includes forming a sacrificial metal layer over a support substrate, the sacrificial metal layer formed of a metal material, and forming a barrier layer over the sacrificial metal layer, the barrier layer formed of an organic material. The method also includes exposing the sacrificial metal layer to oxygen so as to form a sacrificial metal oxide layer, forming a display unit over the barrier layer, and separating the barrier layer from the support substrate.

Abstract: Provided in a semiconductor device including a substrate, an active region upwardly protruding from the substrate, a plurality of active fins upwardly protruding from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being provided in a second direction that is parallel to the upper surface of the substrate and intersects with the first direction, and an isolation structure provided on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin among the plurality of active fins has a staircase shape, the first active fin being provided on a first edge of the active region in the second direction.

Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the first portion and the second portion of the gate electrode.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

Abstract: Provided is a method of manufacturing a semiconductor optical device, which makes it possible to reduce the thickness of a semiconductor optical device including InGaAsP-based III-V compound semiconductor layers containing at least In and P to a thickness smaller than that of conventional devices, and provide a semiconductor optical device. The method of manufacturing a semiconductor optical device includes a step of forming a semiconductor laminate on the InP growth substrate; a step of bonding the semiconductor laminate to the support substrate formed from a Si substrate, with at least the metal bonding layer therebetween; and a step of removing the InP growth substrate.

Abstract: Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.

Abstract: A method of packaging a semiconductor die includes connecting an interposer frame directly to a substrate, wherein the interposer frame has a plurality of conductive columns. The method further includes attaching the semiconductor die to the substrate in an opening of the interposer frame, wherein the semiconductor die directly contacts the substrate. The method further includes forming a molding compound to fill space between the semiconductor die and the interposer frame. The method further includes removing a portion of the molding compound to expose the plurality of conductive columns. The method further includes forming a redistribution layer directly contacting a top surface of the semiconductor die and a top surface of the interposer frame.

Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

Abstract: A light-emitting device includes: at least one light-emitting element; a first light-transmissive member covering the light-emitting element; a second light-transmissive member covering the first light-transmissive member; and a light-diffusing member in the second light-transmissive member. The light-diffusing member includes hollow particles. The second light-transmissive member has a bottom surface having irregularities due to presence of the light-diffusing member.

Abstract: A quantum dot includes: a core including a first semiconductor nanocrystal, and a shell disposed on the core, the shell including a second semiconductor nanocrystal and a dopant, wherein the first semiconductor nanocrystal includes a Group III-V compound, the second semiconductor nanocrystal includes zinc (Zn), sulfur (S), and selenium, and the dopant includes lithium, a Group 2A metal having an effective ionic radius less than an effective ionic radius of Zn2+, a Group 3A element having an effective ionic radius less than an effective ionic radius of Zn2+, or a combination thereof. Also a method of producing the quantum dot, and a composite, and an electronic device including the quantum dot.

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.

Abstract: A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.

Abstract: A memory cell can include a phase change material layer and a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side. A carbon nitride layer can be on the bit line side surface of the first electrode layer. In some examples, a nonconductive separator material can have a word line end and a bit line end, and can have a portion contacting the phase change material layer. The bit line end surface of the nonconductive separator material can be at least partially free of contact with the carbon nitride layer.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.