Abstract: Methods and systems for a storage environment are provided, including generating a plurality of child (or tetris) write requests to write data for a write request using a plurality of subdivisions of a plurality of logical zones defined for a plurality of zoned solid state drives (ZNS SSDs) of a RAID array, each LZone mapped to one or more logical RAID zone (RZone) of the ZNS SSDs having a plurality of physical zones across a plurality of independent media units of each ZNS SSD; assigning a sequence number to each child (or tetris) write request corresponding to each subdivision, the sequence number indicating an order in which the child (or tetris) write requests are to be processed; and selecting, based on the assigned sequence number, one or more subdivisions for sequentially writing data to one or more RZones of the plurality of ZNS SSDs.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.

Abstract: Methods, systems, and devices for techniques to perform a write operation are described. In response to receiving a sequential write command from a host system, the memory system may determine non-linear offsets for a set of requests for portions of the data. The memory system may determine a first subset of the data that includes data segments having logical addresses with gaps corresponding to the offset between the data segments to store in a first memory device. The memory system may store the first subset in a buffer and program the first subset to the first memory device. Additionally, the memory system may determine a second subset of data that using the offset and may transmit a second set of requests for the second subset of data, which may be stored in the buffer and programmed to a second memory device.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks and a controller configured to write data to a plurality of write destination blocks allocated from the plurality of blocks. The controller is configured to in response to receiving a read command from a host, increment a first counter value corresponding to a first block having a block address allocated to a logical address of read target data specified by the received read command. The controller is configured to read the read target data from the first block or a buffer depending on whether the read target data is readable from the first block, and decrement the first counter value corresponding to the first block. The controller is configured to prohibit processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block.

Abstract: Methods, systems, and devices for transferring memory system data to an auxiliary array are described. A memory system may be configured for transferring information between a relatively volatile memory array and a relatively non-volatile memory array in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transfer the identified information to an auxiliary, non-volatile memory array. Such information may be returned to the relatively volatile memory array to support memory system operation after exiting the reduced power mode.

Abstract: A system includes a plurality of host processors and a plurality of hybrid memory cube (HMC) devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die, and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to implement a memory coherence protocol for data stored in the memory of the plurality of memory die.

Abstract: Method and system are provided for storage optimization for event streaming for multiple consumers. The method provides an entire event stream for storage in a first tier storage and dynamically determines advance portions of the event stream for at least some of the consumers based on a consumer's position index in the event stream. The advance portions are portions of the event stream that will be consumed next by the consumer and the method provides the advance portions of the event stream for storage in second tier storage that has a higher performance than the first tier storage.

Abstract: Methods and systems for a networked storage system are provided. One method includes predicting an IOPS limit for a plurality of storage pools based on a maximum allowed latency of each storage pool, the maximum allowed latency determined from a relationship between the retrieved latency and a total number of IOPS from a resource data structure; identifying a storage pool whose utilization has reached a threshold value, the utilization based on a total number of IOPS directed towards the storage pool and a predicted IOPS limit; detecting a bully workload based on a numerical value determined from a total number of IOPS issued by the bully workload for the storage pool and a rising step function; and implementing a corrective action to reduce an impact of the bully workload on a victim workload.

Abstract: A solid state drive (SSD) is presented herein that includes a plurality of memory dies communicatively arranged in a plurality of communication channels such that each respective memory die is associated with a respective one communication channel of the plurality of communication channels, each respective memory die comprises one or more die regions, and each of the one or more die regions comprises a plurality of physical blocks configured to store data. The SSD further includes a memory controller communicatively coupled to the plurality of memory dies. The memory controller is configured to, upon a first power up of the SSD, determine a parameter of the SSD and for each of the one or more die regions, associate, based on the parameter, a number of physical blocks of the plurality of physical blocks with a block region of a plurality of block regions.

Abstract: A device creates virtual storage bucket to abstract the data and the access from another device, and to secure the access using the IAM and the data using encryption and/or Mojette transform in order to generate encrypted/encoded data and transmits the data to another device. The other device saves the encrypted/encoded data for later transmitting the data to the same first device or another for decryption/decoding.

Abstract: A memory system includes a first nonvolatile memory, a first processor, and a second processor. The first processor sets a first assignment amount. The second processor performs access to the first nonvolatile memory, calculates a consumed amount which is an amount according to an operation time of the first nonvolatile memory in the access, and transmits a notification to the first processor when the consumed amount reaches the first assignment amount.

Abstract: According to one or more embodiments of the present invention, a computer implemented method includes receiving, at a secure interface control of a computer system, an access request for a data structure related to a secure entity in a secure domain of the computer system. The secure interface control can check for a virtual storage address associated with a location of the data structure. The secure interface control can request an address translation using a virtual address space of a non-secure entity of the computer system based on determining that the location of the data structure is associated with the virtual storage address. The secure interface control can access the data structure based on a result of the address translation.

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.

Abstract: In a memory controller for controlling a memory device including a memory block coupled to a plurality of word lines, the memory block including a plurality of memory cells respectively coupled to the plurality of word lines, the memory controller comprising: an operating time calculator configured to calculate program operating times taken to perform a program operation on the memory cells respectively coupled to the plurality of word lines; and an operating voltage determiner configured to determine an erase voltage to be used to erase a memory block by comparing a first program operating time, among the program operating times calculated by the operating time calculator, with the other program operating times, except the first program operating time, among the program operating times.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: Data storage systems, devices and methods may use a switch board configured to communicate using a high-speed multi-level signaling protocol, and a midplane having one or more multi-protocol storage device connectors configured to couple the midplane to one or more storage devices, wherein the midplane may be coupled to the switch board and configured to enable the one or more storage devices to communicate with the switch board through the one or more multi-protocol storage device connectors using the high-speed multi-level signaling protocol. The midplane may be coupled to the switch board through one or more high-speed connectors. One or more re-timers may be coupled between one or more of the high-speed connectors and one or more of the multi-protocol storage device connectors. One or more cables may be used to transfer data to and from the multi-protocol storage device connectors.

Abstract: Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information.

Abstract: Various embodiments are provided for enabling data compression in a computing system by a processor. Each storage block of a storage device associated with a queue may be split. Compression of data may be activated upon data occupancy within a queue exceeding a dynamic threshold. In one aspect, only a partial amount of the data is fetched, back to back, from a divided storage block in the storage block according to the queue based upon the data occupancy within the queue exceeding the dynamic threshold. A complete amount of the data may be fetched from the divided storage block in a storage block according to the queue upon the data occupancy within the queue being less than dynamic threshold.