Patents Examined by Michelle T Bechtold
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Patent number: 11314446Abstract: A processing device includes a system tag data structure to store a system tag that includes a logical transfer unit (LTU) identifier corresponding to an LTU, which includes a subset of a plurality of sequential logical block addresses (LBAs) that includes an LBA of a read request, and a mapping data structure that maps a zone of LBA space to physical address space. Hardware logic is to: retrieve the LTU identifier from the system tag; determine a zone identifier (ID) based on the LTU identifier; index, using at least one of the zone ID or the LTU identifier, into the mapping data structure to retrieve metadata that specifies a mapping between the LTU identifier and a physical address of the physical address space; and store the metadata in the system tag data structure in association with the system tag.Type: GrantFiled: June 25, 2020Date of Patent: April 26, 2022Assignee: Micron Technology, Inc.Inventor: Johnny A. Lam
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Patent number: 11307992Abstract: The invention introduces a method for performing operations to namespaces of a flash memory device, at least including the steps: receiving a namespace setting-update command from a host, requesting to update a namespace size of a namespace; determining whether the updated namespace size of the namespace can be supported; and when the updated namespace size of the namespace can be supported, updating a logical-physical mapping table of the namespace to enable the namespace to store user data of the updated namespace size.Type: GrantFiled: October 18, 2018Date of Patent: April 19, 2022Assignee: SILICON MOTION, INC.Inventor: Sheng-Liu Lin
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Patent number: 11294586Abstract: A method for performing read acceleration, an associated data storage device and controller thereof are provided, where the method is applicable to the data storage device and the controller. The method includes: receiving a write command from a host device, and performing programming on a non-volatile (NV) memory element within a plurality of NV memory elements according to the write command; recording operation command-related information corresponding to the write command; when a read command having high priority exists in a queue corresponding to the NV memory element, suspending performing programming on the NV memory element; executing the read command; and after executing the read command, continuing performing programming on the NV memory element at least according to the operation command-related information.Type: GrantFiled: January 17, 2019Date of Patent: April 5, 2022Assignee: Silicon Motion, Inc.Inventors: Che-Wei Hsu, Hsin-Hsiang Tseng
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Patent number: 11287126Abstract: A system for controlling a boiler in a power plant to ensure combust under optimized conditions is provided. The system for controlling an operation of the boiler may include an optimizer configured to perform a combustion optimization operation for the boiler using a boiler combustion model to calculate an optimum control value for at least one control object of the boiler, and an output controller configured to receive the calculated optimum control value from the optimizer and control the control object according to the optimum control value.Type: GrantFiled: September 11, 2019Date of Patent: March 29, 2022Assignee: Doosan Heavy Industries & Construction Co., LtdInventors: Jwa Young Maeng, Sang Gun Na
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Patent number: 11281542Abstract: A backup manager for providing backup services includes storage and a backup orchestrator. The storage stores manager associations. The backup orchestrator obtains a request to provide the backup services for a deployment; in response to the request: identifies types of managers of the deployment; makes a determination, based on the types of the managers of the deployment, that the managers of the deployment require a hybrid backup using the manager associations; and schedules a hybrid backup for the deployment based on the determination.Type: GrantFiled: October 18, 2019Date of Patent: March 22, 2022Assignee: EMC IP HOLDING COMPANY LLCInventors: Sonali Sengupta, Amarendra Behera, Sunil Yadav, Shelesh Chopra, Sapna Chauhan
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Patent number: 11275688Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.Type: GrantFiled: December 2, 2019Date of Patent: March 15, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Sriram Srinivasan, John Kelley, Matthew Schoenwald
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Patent number: 11269776Abstract: Techniques for providing a direct IO path to compressed data on storage media of a storage system. The techniques include triggering a transaction cache to perform a flush operation for updating mapping metadata for a storage object containing the compressed data. Having updated the mapping metadata for the storage object, the techniques further include issuing, by a copier module, an IO read request for the compressed data of the storage object to a namespace layer, which issues the IO read request to a mapping layer. The techniques further include forwarding the IO read request to a logical layer of the mapping layer, bypassing the transaction cache. The techniques further include reading, by the logical layer, the compressed data of the storage object from the storage media, and providing, via the mapping layer and the namespace layer, the compressed data to the copier module for transfer to a destination storage system.Type: GrantFiled: October 17, 2019Date of Patent: March 8, 2022Assignee: EMC IP Holding Company LLCInventors: Xiangping Chen, Philippe Armangau, Anton Kucherov, Xunce Zhou, William C. Davenport
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Patent number: 11269528Abstract: A data storage device may include: a memory array comprising a plurality of blocks, each block including a plurality of pages and a controller in communication with the memory array and comprising a memory buffer, the controller configured to maintain attribute information associated with each block and each page of the memory array, the controller further configured to read data from a requested page in the memory array responsive to an external request, store the read data in a first region of the memory buffer to output the read data responsive to the external request, and copy the read data from the first region of the memory buffer into a second region of the memory buffer upon a determination based on the attribute information that the requested page is included in a supposed-to-be-erased region.Type: GrantFiled: November 6, 2019Date of Patent: March 8, 2022Assignee: SK hynix Inc.Inventor: Jin Pyo Kim
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Patent number: 11262952Abstract: Writing new data to a tape volume of a tape emulation unit includes determining if the new data is an update to data that was previously written, writing the new data to a new section of the tape emulation unit in response to the new data not updating data that was previously written, deleting the data that was previously written and writing the new data to a new section in response to the new data updating data that was previously written, the new data being larger than the data that was previously written, and the underlying file system not supporting variable size records/blocks, and overwriting the data that was previously written in response to the new data updating data that was previously written and either the new data not being larger than the data that was previously written or the underlying file system supporting variable size records/blocks.Type: GrantFiled: July 19, 2019Date of Patent: March 1, 2022Assignee: EMC IP Holding Company LLCInventors: Douglas E. LeCrone, Larry McCloskey, Richard Goodwill, Martin Feeney
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Patent number: 11243705Abstract: A method and system for policy class based data migration. Specifically, the method and system disclosed herein entail dynamically changing policy classes with which any given data migration may be associated while the given data migration is transpiring. In transitioning between policy classes, different levels of resources, available to different policy classes, respectively, may be allocated to supporting the given data migration.Type: GrantFiled: August 1, 2019Date of Patent: February 8, 2022Assignee: EMC IP Holding Company LLCInventors: Jayanth Kumar Reddy Perneti, Rahul Deo Vishwakarma
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Patent number: 11232033Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.Type: GrantFiled: August 2, 2019Date of Patent: January 25, 2022Assignee: Apple Inc.Inventors: Wolfgang H. Klingauf, Connie W. Cheung, Rohit K. Gupta, Rohit Natarajan, Vanessa Cristina Heppolette, Varaprasad V. Lingutla, Muditha Kanchana
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Patent number: 11226760Abstract: Techniques for supporting large segments when issuing writes to an erasure coded storage object in a distributed storage system are provided. In one set of embodiments, a node of the system can receive a write request for updating a logical data block of the storage object, write data/metadata for the block to a record in a data log of a metadata object of the storage object (where the metadata object is stored on a performance storage tier), and determine whether the data log has accumulated a threshold number of records. If so, the node can further allocate an in-memory bank, place the data from the data log records into free slots of the bank, allocate a segment in a capacity object of the storage object for holding contents of the bank (where the capacity object is stored on a capacity storage tier), and write the bank contents via a full stripe write to the allocated segment.Type: GrantFiled: April 7, 2020Date of Patent: January 18, 2022Assignee: VMware, Inc.Inventors: Wenguang Wang, Vamsi Gunturu
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Patent number: 11210024Abstract: A computer-implemented method according to one embodiment includes initiating a read-modify-write (RMW) operation; assigning the RMW operation to a thread; identifying a storage device associated with the RMW operation; assign a log block within the storage device to the thread; determining a free shadow block location within the storage device; creating a copy of data to be written to the storage device during the RMW operation; writing the copy of the data to the free shadow block location within the storage device; updating the log block within the storage device to point to the free shadow block location to which the copy of the data is written; and writing the data to one or more blocks of a home area of the storage device.Type: GrantFiled: December 16, 2019Date of Patent: December 28, 2021Assignee: International Business Machines CorporationInventors: Zhenxing Han, Robert Michael Rees, Steven Robert Hetzler, Veera W. Deenadhayalan
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Patent number: 11204718Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.Type: GrantFiled: September 27, 2019Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Rajesh Sundaram, Zion S. Kwok, Muthukumar Swaminathan
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Patent number: 11199968Abstract: A technique operates multiple data storage tiers including a solid state drive (SSD) storage tier having SSD storage components and a hard disk drive (HDD) storage tier having magnetic disk devices. The technique involves establishing write quotas for the SSD storage components of the SSD storage tier. Each write quota identifies an amount of data that is permitted to be written to a respective SSD storage component during a predefined amount of time. The technique further involves consuming the write quotas in response to write operations performed on the SSD storage components of the SSD storage tier. The technique further involves, in response to a particular write quota for a particular SSD storage component of the SSD storage tier becoming fully consumed, performing a set of remedial activities on the multiple storage tiers to protect operation of the particular SSD storage component of the SSD storage tier.Type: GrantFiled: October 26, 2017Date of Patent: December 14, 2021Assignee: EMC IP Holding Company LLCInventor: Nickolay Alexandrovich Dalmatov
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Patent number: 11182284Abstract: A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module control device. The module control device is configured to read data from the non-volatile memory subsystem in response to a set of signals received from the memory channel indicating a non-volatile memory access request to transfer the data from the non-volatile memory subsystem to the volatile memory subsystem, and to provide at least a portion of the data to the volatile memory subsystem in response to receiving a dummy write memory command including a memory address related to the non-volatile memory access request via the memory channel. The volatile memory subsystem is further configured to receive the dummy write memory command and to receive the at least a portion of the first data in response to the dummy write memory command.Type: GrantFiled: February 5, 2019Date of Patent: November 23, 2021Assignee: Netlist, Inc.Inventor: Hyun Lee
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Patent number: 11176054Abstract: According to one or more embodiments of the present invention, a computer implemented method includes receiving, at a secure interface control of a computer system, an access request for a data structure related to a secure entity in a secure domain of the computer system. The secure interface control can check for a virtual storage address associated with a location of the data structure. The secure interface control can request an address translation using a virtual address space of a non-secure entity of the computer system based on determining that the location of the data structure is associated with the virtual storage address. The secure interface control can access the data structure based on a result of the address translation.Type: GrantFiled: March 8, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Claudio Imbrenda, Christian Borntraeger, Lisa Cranton Heller, Fadi Y. Busaba, Jonathan D. Bradbury
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Patent number: 11175836Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.Type: GrantFiled: February 27, 2020Date of Patent: November 16, 2021Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar
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Patent number: 11176042Abstract: A method and apparatus for monitoring cache transactions in a cache of a data processing system is provided. Responsive to a cache transaction associated with a transaction address, when a cache controller determines that the cache transaction is selected for monitoring, the cache controller retrieves a pointer stored in a register, determines a location in a log memory from the pointer, and writes a transaction identifier to the determined location in the log memory. The transaction identifier is associated with the transaction address and may be a virtual address, for example. The pointer is updated and stored to the register. The architect of the apparatus may include a mechanism for atomically combining data access instructions with an instruction to commence monitoring.Type: GrantFiled: May 21, 2019Date of Patent: November 16, 2021Assignee: Arm LimitedInventors: Curtis Glenn Dunham, Jonathan Curtis Beard, Pavel Shamis, Eric Ola Harald Liljedahl
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Patent number: 11176053Abstract: The disclosure herein describes enabling use of a logical unit for data storage in a distributed storage system using a plurality of backend data objects. Based on receiving instructions to create a logical unit of a logical unit size, a target backend object size to be used with the logical unit is determined, and a plurality of backend objects for allocation to the logical unit is calculated. The backend objects are allocated to the logical unit and a metadata mapping associated with the logical unit is generated. The metadata mapping associates logical block addresses of the logical unit to the allocated backend objects. The logical unit is linked with the metadata mapping in an input/output (I/O) service and, based on the linked metadata mapping, I/O traffic is routed to and from the logical unit. Using multiple backend objects enhances flexibility and efficiency of data storage on the distributed storage system.Type: GrantFiled: October 15, 2019Date of Patent: November 16, 2021Assignee: VMware, Inc.Inventors: Yang Yang, Zhaohui Guo, Haitao Zhou, Zhou Huang, Jian Zhao, Jin Feng