Abstract: A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.

Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.

Abstract: A memory system includes a memory device including first memory blocks each including a memory cell storing a 1-bit data, and second memory blocks each including a memory cell storing a multi-bit data. The memory system further includes a controller configured to estimate data input/output speed of an operation requested by an external device and to determine, based on the estimated data input/output speed, a buffering ratio of pieces of buffered data, temporarily stored in the first memory blocks, to pieces of inputted data. The controller uses the buffer ratio to determine whether to program pieces of inputted data into the second memory blocks directly or to buffer the inputted data in the first memory blocks before programming it into the second memory blocks.

Abstract: Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.

Abstract: Distributed computing system functionality is enhanced. Transmission of data changes may be incremental, thus reducing bandwidth usage and latency. Data changes may be propagated over geographic distances in an outward-only manner from a central data store to one or more servers or other remote nodes, using proactive updates as opposed to making cache updates only in reaction to cache misses. Cache expiration and eviction may be reduced or avoided as mechanisms for determining when cached data is modified. A central computing environment may proactively push incremental data entity changes to place them in remote data stores. Remote nodes proactively check their remote data store, find changes, pull respective selected changes into their remote node caches, and provide current data in response to service requests. Data may be owned by particular tenants. Data pulls may be limited to data in selected categories, data of recently active tenants, or both.

Abstract: Disclosed is a computer implemented method to mark data as persistent using spare bits. The method includes receiving, by a memory system, a set of data, wherein the set of data includes a subset of meta-bits, and the set of data is received as a plurality of transfers, and wherein the memory system includes a first rank and a second rank. The method also includes decoding, by a decoder, the subset of meta-bits, wherein the subset of meta-bits are configured to indicate the set of data is important. The method further includes storing, based on the decoding, the set of data in a persistent storage medium.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller prohibits processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block, on the basis of a plurality of first counter values corresponding to a plurality of blocks in the nonvolatile memory. The controller prohibits release of a region in a buffer that stores data being written or waiting for being written to a write destination block associated with an uncompleted read command, on the basis of a plurality of second counter values corresponding to a plurality of write destination blocks.

Abstract: Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data elements stored in a first data storage location that are being transferred to a second data storage location. For each group of one or more of the data elements in the sequence, a value of a buffer assignment element that can be switched between multiple values each corresponding to a different one of the memories is identified. A buffer memory address for the group of one or more data elements is determined based on the value of the buffer assignment element. The value of the buffer assignment element is switched prior to determining the buffer memory address for a subsequent group of one or more data elements of the sequence of data elements.

Abstract: A data storage system operates a file system as a thinly provisioned file system having a host-visible virtual space and a smaller allocated space of underlying physical storage from a pool. The file system applies formatting to the allocated space and utilizes formatted allocated space for storing host files. The file system receives a file I/O request that requires increasing the allocated space of the file system, and in response (1) obtains an extent of physical storage from the pool and adds it to the file system as added allocated space, and (2) formats an initial portion of the added allocated space and satisfies the file I/O request using the formatted initial portion. Over a subsequent period the file system incrementally formats additional portions of the added allocated space and satisfies subsequent file I/O requests from the added portions.

Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.

Abstract: In a storage device having an improved data receiving rate, the storage device includes: a plurality of memory devices each including a plurality of select signal pads; and a memory controller for providing a plurality of select signals representing a selected memory device among the plurality of memory devices through the plurality of select signal pads, wherein some select signals among the plurality of select signals include stack information indicating a number of the plurality of memory devices controlled by the memory controller.

Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks in cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.

Abstract: The present disclosure provides techniques for managing a cache of a computer system using a cache management data structure. The cache management data structure includes a cold queue, a ghost queue, and a hot queue. The techniques herein improve the functioning of the computer because management of the cache management data structure can be performed in parallel with multiple cores or multiple processors, because a sequential scan will only pollute (i.e., add unimportant memory pages) cold queue, and to an extent, ghost queue, but not hot queue, and also because the cache management data structure has lower memory requirements and lower CPU overhead on cache hit than some prior art algorithms.

Abstract: By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.

Abstract: A computer-implemented method to identify redundant Input/Output (I/O) queues in a multi-site storage system. The method includes receiving, from a host, by a backup storage system, a request to process a first set of Input/Output (I/O) queues, wherein the backup storage system is a second subsystem in a multi-site storage system. The method includes, allocating memory on the backup storage system. The method includes, identifying a second set of I/O queues established at a primary storage system, a first subsystem in the multi-site storage system. The method includes, determining the first set of I/O queues and the second set of I/O queues are redundant. The method includes, responsive to determining queues are redundant: notifying via the host, that the first set of the redundancy, terminating a connection between the host and the backup storage system, and de-allocating the memory to process the first set of I/O queues.

Abstract: Various systems and methods for memory management are described herein. A system for managing memory includes a memory management unit to: receive an indication of a memory allocation request; identify a memory region to satisfy the memory allocation request; determine whether the memory region has a tracking record in a tracking data structure, the tracking data structure configured to track whether a particular memory region has any references pointing to it; and revise the tracking record in the tracking data structure when the memory region has the tracking record.

Abstract: Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.

Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks demoted from cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.

Abstract: A system and method for metadata storage includes use of a storage controller to receive a write operation from a host, create a metadata entry for storing metadata associated with data written by the write operation, and store the metadata entry into a metadata store. The metadata store includes a plurality of active partitions, a plurality of inactive partitions, and a queue identifying locations in the active partitions where the metadata entry may be stored. The metadata store is further used to access data written to one or more storage devices. Storing the metadata entry into the metadata store includes popping a first location from the queue, identifying a first active partition from the active partitions based on the first location, and storing the metadata entry in the first active partition. In some embodiments, each of the active partitions may be organized into two or more tiers.

Abstract: A memory controller controls access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller allocates a physical block within the flash memory in a prescribed search range as a prescribed physical block where management information is written, writes the management information necessary for accessing the flash memory to the prescribed physical block, and operates to search for the prescribed physical block when second firmware is read from the flash memory. The writing information, including the management information, is written to the prescribed physical block in a same format regardless of a type of flash memory. Information written to pages is sequentially read at prescribed page intervals in the prescribed search range in searching for the prescribed physical block.