Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.

Abstract: An array substrate includes an active layer including a channel region, a gate electrode positioned corresponding to the channel region, and a gate insulating film between the active layer and the gate electrode. The gate electrode includes a transparent conductive film and an opaque conductive film, and the transparent conductive film is between the channel region and the opaque conductive film.

Abstract: A process for producing high performance organic thin film transistors in which the molecules in the organic thin film are highly ordered and oriented to maximize the mobility of current charge carriers. The uniform monolayer surface over various substrate materials so formed, result in a more reproducible and readily manufacturable process for higher performance organic field effect transistors that can be used to create large area circuits using a range of materials.

Abstract: A light emitting device which is capable of suppressing deterioration by diffusion of impurities such as moisture, oxygen, alkaline metal and alkaline earth metal, and concretely, a flexible light emitting device which has light emitting element formed on a plastic substrate. On the plastic substrate, disposed are two layers and more of barrier films comprising a layer represented by AlNxOy which is capable of blocking intrusion of moisture and oxygen in a light emitting layer and blocking intrusion of impurities such as an alkaline metal and an alkaline earth metal in an active layer of TFT, and further, a stress relaxation film containing resin is disposed between two layers of barrier films.

Abstract: A light-emitting device of an embodiment of the present application comprises a semiconductor layer sequence provided with a first main side, a second main side, and an active layer; a beveled trench formed in the semiconductor layer sequence, having a top end close to the second main side, a bottom end, and an inner sidewall connecting the top end and the bottom end. In the embodiment, the inner sidewall is an inclined surface. The light-emitting device further comprises a dielectric layer disposed on the inner sidewall of the beveled trench and the second main side; a first metal layer formed on the dielectric layer; a carrier substrate; and a first connection layer connecting the carrier substrate and the semiconductor layer sequence.

Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.

Abstract: In a light emitting device, a light emitting device unit, and a method for fabricating a light emitting device according to an embodiment of the present invention, a light emitting device (100) includes a substrate (131), a semiconductor light emitting element (121) disposed on the substrate (131), and a resistor (122) coupled to the semiconductor light emitting element (121). The resistor (122) is coupled in parallel to the semiconductor light emitting element (121). The resistor (122) has a resistance set at such a value that when a light emitting operation voltage for causing light emission of the semiconductor light emitting element (121) is applied to the semiconductor light emitting element (121), a current flowing through the resistor (122) is equal to or less than one-fiftieth of a current flowing through the semiconductor light emitting element (121).

Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package enables a narrow viewing angle without requiring a second lens. In particular, the PLCC package is provided with a reflector cup having multiple stages where the geometry or some other characteristic of one stage is different from the geometry or some other characteristic of another stage.

Abstract: The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.

Abstract: A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a second direction different to the first direction, such that the wires of the first and second metal layers appear from above or below to form virtual intersections. Vias or contacts are coupled between the first and second metal layers and configured to route signals between the first and second metal layers. Pins are coupled to the first metal layer and configured to provide input signals or receive output signals from a standard cell, the pins being positioned along the wires in the first metal layer so as to be spaced from the virtual intersections.

Abstract: A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 ?m; and an n-electrode pad formed on the n-type nitride semiconductor layer.

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract: An optical integrated semiconductor light emitting device with improved light emitting efficiency is provided by preventing leak current from flowing through a high defect region of the substrate. The optical integrated semiconductor light emitting device includes: a substrate, in which in a low defect region made of crystal having a first average dislocation density, one or more high defect regions having a second average dislocation density higher than the first average dislocation density are included; and a Group III-V nitride semiconductor layer which is formed on the substrate, has a plurality of light emitting device structures, and has a groove in the region including the region corresponding to the high defect region (high defect region).

Abstract: A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular layer including a monolayer of organic molecules and a source of water molecules is established in the junction. Upon introduction of a forward bias, the molecular layer facilitates a redox reaction between the electrodes, thereby reducing a tunneling gap between the electrodes.

Abstract: A sensor capable of detecting detection targets that are necessary to be detected with high sensitivity is provided. It comprises a field-effect transistor 1A having a substrate 2, a source electrode 4 and a drain electrode 5 provided on said substrate 2, and a channel 6 forming a current path between said source electrode 4 and said drain electrode 5; wherein said field-effect transistor 1A comprises: an interaction-sensing gate 9 for immobilizing thereon a specific substance 10 that is capable of selectively interacting with the detection targets; and a gate 7 applied a voltage thereto so as to detect the interaction by the change of the characteristic of said field-effect transistor 1A.

Abstract: A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide material and a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a copper species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic.

Abstract: According to the present invention, there is provided a method for manufacturing an SOI wafer, the method configured to grow an epitaxial layer on an SOI layer of the SOI wafer having the SOI layer on a BOX layer to increase a thickness of the SOI layer, wherein epitaxial growth is carried out by using an SOI wafer whose infrared reflectance in an infrared wavelength range of 800 to 1300 nm falls within the range of 20% to 40% as the SOI wafer on which the epitaxial layer is grown. As a result, a high-quality SOI wafer with less slip dislocation and others can be provided with excellent productivity at a low cost as the SOI wafer including the SOI layer having a thickness increased by growing the epitaxial layer, and a manufacturing method thereof can be also provide.

Abstract: A device comprises a substrate having at least one active region, an insulating layer above the substrate, and an electrode in a gate electrode layer above the insulating layer, forming a metal-oxide-semiconductor (MOS) capacitor. A first contact layer is provided on the electrode, having an elongated first pattern extending in a first direction parallel to the electrode. A contact structure contacts the substrate. The contact structure has an elongated second pattern extending parallel to the first pattern. A dielectric material is provided between the first and second patterns, so that the first and second patterns and dielectric material form a side-wall capacitor connected in parallel to the MOS capacitor.