Abstract: A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device.

Abstract: A system for mask design repair may develop a simulation-based model of a layer thickness after one or more process steps for fabricating features on a sample, develop a transformed model of the fabrication process that emulates the simulation-based model and has a faster evaluation speed than the simulation-based model, and where the inputs to the transformed model include the input mask design, and where the outputs of the transformed model include one or more output parameters associated with fabrication of the input mask design as well as one or more sensitivity metrics describing sensitivities of the one or more output parameters to variations of the input mask design. The system may further receive a candidate mask design and generate a repaired mask design based on the transformed model and the candidate mask design.

Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.

Abstract: Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.

Abstract: A battery management system for use in charging a rechargeable battery is disclosed. The battery management system comprises a controller powered by a first power supply, at least one sensor for providing a sensor signal relating to at least one parameter of the rechargeable battery to the controller, and a data store. The controller is configured to write data to the data store based on the sensor signal. The data store is coupled to a data reader. The data reader is operable to be powered by an auxiliary power supply to read data held by the data store.

Abstract: A power supply is disclosed for an industrial control system or any system including a distributed power supply network. In embodiments, the power supply comprises: a battery module including a battery cell and a battery monitor configured to monitor the battery cell; and a self-hosted server operatively coupled with the battery module, the self-hosted server being configured to receive diagnostic information from the battery monitor and provide network access to the diagnostic information. In implementations, the diagnostics stored by the self-hosted server can be broadcast to or remotely accessed by enterprise control/monitoring systems, application control/monitoring systems, or other remote systems via a secured network (e.g., secured access cloud computing environment).

Abstract: An early warning method for safety production risk of tailings pond based on risk ranking is provided. The early warning method includes: monitoring and collecting internal basic data of a tailings pond in real-time, and performing a basic monitoring and a basic early warning; collecting geographical location data, meteorological data, and historical geological disaster data of an area where the tailings pond is located; performing risk ranking on a safety production risk of the tailings pond, thereby obtaining a risk level of the tailings pond; and collecting case data of global tailings pond accidents and hazard degree data thereof, acquiring accident solution strategies for the global tailings pond accidents, performing management and monitoring on the tailings pond, setting parameters in a process of the basic monitoring, and performing a ranked early warning on the safety production risk of the tailings pond based on the risk level.

Abstract: Provided is a method of controlling a battery pack, and a battery pack controlled by the method. A battery pack includes a plurality of slave battery modules, each of the slave battery modules including a battery that includes at least one battery cell and a slave controller that is configured to control charge and discharge of the battery, a master battery module including a master controller that is configured to control the slave controller, and a communication cable having formed thereon a first port to which the master controller is connected and a plurality of second ports to which the slave controller is connected. The first port includes an identification terminal configured to output an identification signal which is an electrical signal corresponding to the number of the second ports. A method of controlling the battery pack is provided.

Abstract: Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Abstract: The present application provides a device battery and an unmanned aerial vehicle (UAV). The device battery includes: a battery microprocessor, an electrically erasable programmable read-only memory and a marking component. The battery microprocessor is connected to the electrically erasable programmable read-only memory, and the marking component is connected to the battery microprocessor and the electrically erasable programmable read-only memory. The marking component is configured to mark a storage address to which battery data is written last time. The battery microprocessor is configured to write battery data to the electrically erasable programmable read-only memory in a cyclic erasing writing mode according to the storage address currently marked by the marking component. According to the solution, an independent electrically erasable programmable read-only memory is added inside the device battery to store the battery data, which can improve stability and safety of battery data storage.

Abstract: A Protective Earth (PE) loss detection method for charging an electrical vehicle is provided. The electrical vehicle comprises an Electrical Vehicle Supply Equipment (EVSE), a charging connector, and/or a charging cable comprising at least a Proximity Pilot (PP) line for a PP signal, a Control Pilot (CP) line for a CP signal and a PE line for a PE signal. The method comprises detecting interruption of the PE line by observing a change of the PP signal.

Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

Abstract: The invention offers an ultracapacitor-based power system solution with four main functional blocks which are power conditioning block, monitoring block, charge-discharge block and protection block. The proposed system has the advantage of working well in the environment of vibration, high temperature, has a large capacity to provide a large amount and radiates less heat compared to systems using traditional batteries. In addition, the system has functions to protect and stabilize the output voltage, and the operating parameters of the system is monitored continuously.

Abstract: Loss reduction methods are described. A first transmission loss associated with signal transmission through a trace in a first circuit board design is determined. The trace is routed from an integrated circuit disposed on a circuit board to a circuit element disposed on the circuit board. It is determined that the first transmission loss is greater than a threshold transmission loss. The first circuit board design is altered to obtain a second circuit board design. In the second circuit board design, the trace is routed from the integrated circuit to a connector disposed on the circuit board, and the connector is electrically coupled to the circuit element by a cable. A second transmission loss associated with signal transmission between the integrated circuit and the circuit element in the second circuit board design is less than the threshold transmission loss.

Abstract: In an inverter generator controller, residual charge of a battery is detected and generated power output is detected. Then, low-load charging of the battery is implemented if the detected generated power output of the engine generator unit is equal to or greater than the detected load output demand and the detected generated power output of the engine generator unit is less than the predetermined low-load value a, when the detected residual charge of the battery is equal to or less than the first threshold value. When the detected residual charge of the battery becomes greater than the first threshold value, the low-load charging of the battery is terminated.

Abstract: Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A sensor arrangement for a vehicle storage system for electric energy is disclosed. The vehicle storage system includes a plurality of storage units for electric energy that are connected in series between a reference voltage node and a first or a second output terminal to provide electric energy to at least one consumer at the first or at the second output terminal. The sensor arrangement has a plurality of sensor units configured to determine charging levels of the storage units by measuring at least one of the following quantities: one or more voltages between reference voltage node and a node between adjacent storage units, one or more voltage drops over at least a subset of the storage units, electric currents though the first and/or through second output terminal, or temperatures of the storage units.

Abstract: Example wireless charging systems and methods are disclosed. One example system includes a receive end and a transmit end. The receive end includes a receive coil, a receive end compensation circuit, a rectifier, and a controller. The controller adjusts a phase difference between a first bridge arm and a second bridge arm of the rectifier, and adjusts a phase-shift angle between a bridge arm voltage of the rectifier and a fundamental component of an input current of the rectifier, so that zero-voltage switching is implemented for controllable switching transistors of the rectifier. An inductance compensation module may weaken a capacitive part of the equivalent impedance, and reduce reactive power of the wireless charging system.