Abstract: The invention relates to a system for indicating information representing battery status of an electronic device. The system comprises a charging unit and an electronic device. The charging unit comprises charging means, wireless communication means, and indication means. The electronic device comprises a rechargeable battery, charging means, and wireless communication means. During the wireless charging of the electronic device, the electronic device is configured to detect information representing the battery status of said electronic device and to communicate the detected information representing the battery status to the charging unit, and the charging unit is configured to receive the information from the electronic device and to indicate at least part of the received information representing the battery status of the electronic device. The invention relates also to a method for indicating information representing battery status of an electronic device.

Abstract: A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.

Abstract: An energy storage apparatus includes: a plurality of energy storage devices connected in series; a voltage detection unit that detects voltages of the plurality of energy storage devices; a discharge circuit that discharges the energy storage devices; and a control unit. The energy storage devices include lithium ion cells. The plurality of energy storage devices is chargeable by an external charger for a lead-acid battery, wherein a charge voltage per cell of the external charger for the lead-acid battery is higher than a maximum voltage of the energy storage device, and wherein the control unit discharges only an energy storage device having a highest voltage out of the plurality of energy storage devices when the plurality of energy storage devices is charged by a charger.

Abstract: A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.

Abstract: A transmission path design assistance system assisting in the design of a transmission path with different reflection specification values for each frequency is obtained.

Abstract: A power tool includes a power tool housing accommodating a motor; a battery pack interface electrically connected to the motor and being configured to be physically and electrically connected to and disconnected from a power tool interface of a battery pack; and a wireless communicator configured to be attached to or detached from the power tool housing. The wireless communicator wirelessly transmits data between the power tool and an external device using radio waves. In addition, the power tool housing includes a receptacle opening configured to accommodate the wireless communicator within the power tool housing such that no part of the wireless communicator projects or protrudes beyond an outer surface or contour of the power tool housing.

Abstract: An electronic device includes a display and an input device. While in wireless communication with a set of peripherals that includes a first peripheral and a second peripheral, and in accordance with a determination that the first peripheral satisfies charging criteria that require that the first peripheral is coupled with the second peripheral, the electronic device: initiates charging of the first peripheral, by the second peripheral, to a first threshold charge level that is less than a charge limit of the first peripheral; and, in accordance with a determination that charging completion criteria for the first peripheral are met: initiates charging of the first peripheral, by the second peripheral, to the charge limit of the first peripheral.

Abstract: Disclosed herein are battery management systems and methods for activating battery override logic for a battery management system to provide a power path to a battery pack. A method of activating battery override logic for a battery management system may comprise detecting a predetermined key toggle sequence performed in a predetermined amount of time or detecting an override message received from a CAN bus. The method may further comprise determining if the last override turn-on sequence was requested more than a predetermined amount of time ago, confirming that the override is configured for the contactor, and turning on the contactor to provide a power path to the battery pack for a limited predetermined amount of time. An exemplary predetermined toggle sequence may comprise on-off-on-off-on performed within 10 seconds. An exemplary override message from the CAN bus may be initiated by a user having a key, code, or access card.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: Analysis of power supply noise in simulations of a design of a circuit can use per instance dynamic voltage drops (DVD) in timing analyses so that the simulated DVD values on a per victim cell basis can accurately guide the timing analysis on each victim instead of a global DVD for all victims during the timing analysis. In one embodiment, a method can: determine, during a power analysis simulation, a representation of an energy lost, during each switching window at each output of each victim cell, at one or more power supply rails of each of the victim cells in the set of victim cells due to aggressors in the design; and provide the representation of the energy lost separately for each victim cell to a timing analysis system. The representation can be a rectangle having a width defined by a switching window of a victim's output.

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

Abstract: Embodiments herein provide for reverse engineering of integrated circuits (ICs) for design verification. In example embodiments, an apparatus receives a gate-level netlist for an integrated circuit (IC), generates a list of equivalence classes related to signals included in the gate-level netlist, determines control signals of the gate-level netlist based at least in part on the list of equivalence classes, determines a logic flow of a finite state transducer (FST) based at least in part on the control signals, and generates register transfer level (RTL) source code for the IC based on the FST.

Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Abstract: A device includes a first cell, a second cell, and first isolation portions. The second cell is adjacent the first cell. The first and second cells are arranged in a first direction, and the first cell includes first and second conductive structures. The first conductive structures extend in the first direction. Each of the first conductive structures has a first end facing the second cell. The second conductive structures extend in the first direction. The first and second conductive structures are alternately arranged in a second direction different from the first direction. The first isolation portions are respectively abutting the first ends of the first conductive structures. Two of the first isolation portions are misaligned with each other in the second direction.

Abstract: Embodiments provide for building a global clock tree. In embodiments, an example method includes inserting clock drivers at symmetric locations in one or more hierarchy levels of a plurality of hierarchy levels of an integrated circuit (IC) design. The example method further includes generating one or more routes by routing one or more nets within or across the one or more hierarchy levels of the plurality of hierarchy levels. The example method further includes matching symmetric routes of the one or more routes at each of the one or more hierarchy levels irrespective of a number of physical hierarchies each associated net spans. The example method further includes placing one or more ports at one or more signal entry points where routes of the one or more routes cross physical hierarchy blocks.

Abstract: Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units.

Abstract: A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.

Abstract: The disclosed method is applicable to a many-core system. The method includes: acquiring multiple pieces of .routing information, each of which includes two logical nodes and a data transmission amount between the two logical nodes; determining a piece of unprocessed routing information with a maximum data transmission amount as current routing information; mapping each unlocked logical node of the current routing information to one unlocked processing node, and locking the mapped logical node and processing node, wherein if there is an unlocked edge processing node, the unlocked logical node is mapped to the unlocked edge processing node; and returning, if there is at least one unlocked logical node, to the step of determining the piece of unprocessed routing information with the maximum data transmission amount as the current routing information.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: A process of selecting a measurement location, the process including: obtaining pattern data describing a pattern to be applied to substrates in a patterning process; obtaining a process characteristic measured during or following processing of a substrate, the process characteristic characterizing the processing of the substrate; determining a simulated result of the patterning process based on the pattern data and the process characteristic; and selecting a measurement location for the substrate based on the simulated result.