Abstract: A method is disclosed for storing and reusing the PC description of layout cells. A database stores predefined cells and PC descriptions that were previously calculated by a 3D field solver. Regarding a candidate cell from the layout diagram, the database is searched for a substantial match amongst the predefined cells. If there is a match, then the stored PC description of the matching predefined cell is assigned to the candidate cell in the layout diagram, which avoids having to make a discrete calculation for the PC description. If there is no match, then the 3D field solver is applied to the candidate cell in order to calculate the PC description of the candidate cell. To facilitate reusing the newly calculated PC description, the candidate cell and the newly calculated PC description are stored in the database as a new predefined cell and its corresponding PC description.

Abstract: Provided are a terminal device and a method and system for monitoring battery safety in a terminal device. The method includes the following. Power-off information generated upon disconnection between a battery connector of the terminal device and a main board of the terminal device is acquired. Whether the disconnection between the battery connector and the main board is an unauthorized disconnection is determined according to the power-off information. Upon determining that the disconnection between the battery connector and the main board is the unauthorized disconnection, determine that a battery of the terminal device has safety hazard and control the terminal device to send reminder information indicative of battery abnormality.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Generating a circuit layout is provided. A circuit layout associated with a circuit is received. A parallel pattern recognition is performed on the circuit layout. Performing the parallel pattern recognition includes determining that there is a parallel pattern in the circuit layout. In response to determining that there is a parallel pattern in the circuit layout, a cell swap for a first cell associated with the parallel pattern with a second cell is performed. After the cell swap for the first cell, engineering change order routing is performed to connect the second cell in the circuit layout. An updated circuit layout having the second cell is provided.

Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

Abstract: In some embodiments, a client device may obtain an external signal. The hardware components of an integrated circuit of the client device may be reconfigured from a first configuration to a second configuration based on information in the external signal such that one or more portions of the integrated circuit that was previously inaccessible is now accessible and an application may access the one or more portions of the integrated circuit. Further, in response to a trigger, the components of the integrated circuit may reconfigure from the second configuration to the first configuration such that the one or more portions of the integrated circuit is inaccessible.

Abstract: Techniques and a system to facilitate estimation of a quantum phase, and more specifically, to facilitate estimation of an expectation value of a quantum state, by utilizing a hybrid of quantum and classical methods are provided. In one example, a system is provided. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can include an encoding component and a learning component. The encoding component can encode an expectation value associated with a quantum state. The learning component can utilize stochastic inference to determine the expectation value based on an uncollapsed eigenvalue pair.

Abstract: Various implementations of a smart battery management system are provided. An example method includes identifying sensor data of a cell in a battery system; predicting, based on the sensor data, a failure event of the cell; and preventing the failure event by activating a control circuit connected to the cell.

Abstract: Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

Abstract: Disclosed is a method for validating a hardware system by a model thereof, which method comprises: providing reference structures and determining, in the model, sub-structures, each of which is structurally equivalent to one of the reference structures; extracting, from the model, input cones for each sub-structure; creating monopartite candidate graphs by mapping the bipartite sub-structure and the respective input cones to one of the candidate graphs; creating, for each candidate graph, a match vector, each dimension of the match vector comprising a count of occurrences, in the candidate graph, of a different one of predetermined graphlets; clustering, on the basis of similarity of the match vectors, the candidate graphs in clusters; and selecting, from each of the clusters, one candidate graph and determining a functional behaviour of the respective sub-structure of the selected candidate graph for validating the hardware system.

Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

Abstract: A battery-powered tool (200) may include a first tool-side electrical contact (251), a battery detection switch (220), a tool load (300), and a load connection switching device (210). The load connection switching device (210) may be configured to make an electrical connection between the first tool-side electrical contact (251) and the tool load (300) in response to a state change of the battery detection switch (220). The tool (200) may define engagement positions with the battery (110). In the first engagement position, a first battery-side electrical contact (111) is electrically coupled to a first tool-side electrical contact (251), and the battery detection switch (220) is not physically engaged. In the second engagement position, the first battery-side electrical contact (111) is electrically coupled to the tool-side electrical contact (251), and the battery detection switch (220) is physically engaged to cause a state change of the battery detection switch (220).

Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.

Abstract: Aspects of the present disclosure address systems, methods, and a user interface for providing interactive skew group visualizations for integrated circuit (IC) design. The method includes causing display of a user interface that includes a display of a grouped view of a clock-tree including a plurality of skew group indicators. The method further includes receiving a user selection of a skew group indicator and updating the user interface to display a detailed view of the skew group including a graphical representation of each clock sink in the skew group and corresponding timing information. The method further includes receiving a second user selection of a first clock sink and in response, the display is updated to display an indicator of a physical location of the first clock sink within the clock tree.

Abstract: An electronic device is provided. The electronic device includes a housing, a battery included within the housing, a connector electrically connected to an external power supply device including an integrated circuit (IC) and exposed to a part of the housing, and a power management unit included within the housing and electrically connected to the connector, wherein the power management unit is configured to communicate with the IC of the external power supply device, and wherein the connector is configured to receive a first current of a first current value during at least a part of the communication and to receive a second current of a second current value greater than the first current value during at least a part in which the communication is not performed.

Abstract: A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device.

Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

Abstract: A detection unit (231) detects, based on synthesis result data obtained by logic synthesis on design data of a target circuit, a predicted place where a glitch is predicted to occur in the target circuit. An insertion unit (232) inserts a glitch removal circuit in an output side of the predicted place by making a change to at least one of the synthesis result data and the design data.

Abstract: Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.