Abstract: A computer-assisted method for determining a microfluidic circuit configured to reproduce a neuron circuit, and comprising including the following steps: —obtaining a description of the neuron circuit, the description of the neuron circuit comprising a plurality of neuron populations and at least one neuron connection; —determining at least one first parameter for each node of a plurality of nodes of the microfluidic circuit, each node being associated with and configured to receive one neuron population among the plurality of neuron populations of the neuron circuit; —determining at least one second parameter for at least one connection of the microfluidic circuit, each connection being associated with and configured to receive a neuron connection of the at least one neuron connection of the neuron circuit; —determining the positioning of each node of the plurality of nodes and of each connection of the at least one connection.

Abstract: A blender using different charging modes with wireless charging is disclosed. Exemplary implementations may include a base assembly, a container assembly, an electrical motor, a blending component, a control interface, blending control circuitry, charging control circuitry, and/or other components. The base component may include a rechargeable battery and a wireless charging interface. The charging control circuitry may be configured to make different types of detections related to the availability and/or usage of electrical power and related to the usage and alignment of the wireless charging interface with an external charging structure. The charging control circuitry may conduct electrical power to the rechargeable battery using at least two different charging modes, thus providing different amounts of electrical power to the rechargeable battery in different charging modes.

Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.

Abstract: A hierarchical voltage control system is provided. A supercapacitor unit and a lithium battery unit are both connected to a DC bus to form a parallel-structure-type hybrid energy storage system, and are each configured with a power device and a switch to control a connection relationship between the corresponding unit and the DC bus. A detection circuit detects current and voltage values of the supercapacitor unit, the lithium battery unit, and the DC bus, detects an operating parameter of a power conversion system, and transmits the operating parameter to a processor, the power conversion system being connected in parallel to the DC bus for bidirectional power conversion of AC and DC energy sources. A microprocessor determines a system operating condition and uses a hierarchical voltage control strategy to control charging and discharging states of the supercapacitor unit and the lithium battery unit.

Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

Abstract: The present inventions, in one aspect, are directed to techniques and/or circuitry to applying a charge pulse to the terminals of the battery during a charging operation, measure a plurality of voltages of the battery which are in response to the first charge pulse, determine a charge pulse voltage (CPV) of the battery, wherein the charge pulse voltage is a peak voltage which is in response to the first charge pulse, determine whether the CPV of the battery is within a predetermined range or greater than a predetermined upper limit value and adapt one or more characteristics of a charge packet if the CPV is outside the predetermined range or is greater than a predetermined upper limit value.

Abstract: A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: Embodiments of the present application provide an energy storage system and a self-start method thereof. The system includes a power conversion system; a DC bus; n single racks, where n is a natural number, and n is greater than or equal to 1; a host computer, connected to each of the n single racks; and a master battery management unit, connected to each of the n single racks, where each of the n single racks includes a first miniature circuit breaker, a DC/DC power module, a slave battery management unit, a wake-up relay, a main positive high voltage relay, a main negative high voltage relay, a CSC module, and a battery box. The technical solutions provided in the embodiments of the present application can resolve the problem that an energy storage system cannot self-start when there is no external power supply.

Abstract: Computer-implemented systems and methods are described herein for determining mechanical properties of an electronic assembly. An input specification for a model of the electronic assembly is received, wherein the input specification includes a compressible body and a surrounding component in the electronic assembly. A geometric interference between the compressible body and the surrounding component is identified. A displacement is generated for the compressible body to account for the geometric interference. A non-linear contact is then generated between the displaced compressible body and the surrounding component. The model is updated with the displacement and the non-linear contact. Then, a resulting force equilibrium is determined within the electronic assembly based on the updated model, wherein the resulting force equilibrium is determined by removing the displacement from the updated model.

Abstract: A chip design method, a chip design device, a chip, and an electronic device are provided. The chip design method includes: determining at least one power state of the chip, one power state of the at least one power state including switch states of respective power domains on the chip in a chip operation mode, and the at least one power state including a first power state; determining control signals sent by changed power domains in the respective power domains in a case where a power state of the chip is switched to the first power state, in a case where the power state of the chip is switched to the first power state, switch states of the changed power domains changing; and analyzing timing dependency between the control signals to determine timing dependency between power domains to which the control signals act in the first power state.

Abstract: A standard unit (100) for a system on chip design includes a plurality of semiconductor devices and is configured to implement a basic logic function. The standard unit (100) includes a first transistor (110) of a first threshold type and a second transistor (120) of a second threshold type, the second threshold type is different from the first threshold type, wherein a threshold range of the first threshold type is different from that of the second threshold type.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Abstract: A circuit for controlling a battery includes a switch having a source, a gate, a drain, and a first diode. The source is connected to an anode of the first diode. The drain is connected to a cathode of the first diode. The drain is configured to be connected to a positive terminal of the battery. The circuit also includes a second diode. An anode of the second diode is configured to be connected to a negative terminal of the battery. A cathode of the second diode is connected to the source of the switch. The circuit is configured to switch the battery on and off.

Abstract: Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE).

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.

Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition dock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the dock distribution network and the trial timing for the partition dock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.